Commit 17fa0326 authored by Heiko Schocher's avatar Heiko Schocher Committed by Tom Rini

serial, ns16550: bugfix: ns16550 fifo not enabled

commit: 65f83802 "serial: 16550: Add getfcr accessor"
breaks u-boot commandline working with long commands
sending to the board.

Since the above patch, you have to setup the fcr register.

For board/archs which enable OF_PLATDATA, the new field
fcr in struct ns16550_platdata is not filled with a
default value ...

This leads in not setting up the uarts fifo, which ends
in problems, when you send long commands to u-boots
commandline.

Detected this issue with automated tbot tests on am335x
based shc board.

The error does not popup, if you type commands. You need
to copy&paste a long command to u-boots commandshell
(or send a long command with tbot)

Possible boards/plattforms with problems:
./arch/arm/cpu/arm926ejs/lpc32xx/devices.c
./arch/arm/mach-tegra/board.c
./board/overo/overo.c
./board/quipos/cairo/cairo.c
./board/logicpd/omap3som/omap3logic.c
./board/logicpd/zoom1/zoom1.c
./board/timll/devkit8000/devkit8000.c
./board/lg/sniper/sniper.c
./board/ti/beagle/beagle.c
./drivers/serial/serial_rockchip.c
Signed-off-by: 's avatarHeiko Schocher <hs@denx.de>
Signed-off-by: 's avatarLadislav Michl <ladis@linux-mips.org>
Tested-by: 's avatarAdam Ford <aford173@gmail.com>
Reviewed-by: 's avatarTom Rini <trini@konsulko.com>
parent 0675f992
......@@ -45,10 +45,14 @@ void lpc32xx_uart_init(unsigned int uart_id)
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_platdata lpc32xx_uart[] = {
{ .base = UART3_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
{ .base = UART4_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
{ .base = UART5_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
{ .base = UART6_BASE, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
{ .base = UART3_BASE, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART4_BASE, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART5_BASE, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART6_BASE, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
};
#if defined(CONFIG_LPC32XX_HSUART)
......
......@@ -40,14 +40,20 @@ DECLARE_GLOBAL_DATA_PTR;
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_platdata am33xx_serial[] = {
{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
# ifdef CONFIG_SYS_NS16550_COM2
{ .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
{ .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
# ifdef CONFIG_SYS_NS16550_COM3
{ .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
{ .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
{ .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
{ .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK },
{ .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
# endif
# endif
};
......
......@@ -219,6 +219,7 @@ static struct ns16550_platdata ns16550_com1_pdata = {
.base = CONFIG_SYS_NS16550_COM1,
.reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(ns16550_com1) = {
......
......@@ -32,7 +32,8 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct ns16550_platdata igep_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(igep_uart) = {
......
......@@ -31,7 +31,8 @@ const omap3_sysinfo sysinfo = {
static const struct ns16550_platdata serial_omap_platdata = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(sniper_serial) = {
......
......@@ -49,7 +49,8 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct ns16550_platdata omap3logic_serial = {
.base = OMAP34XX_UART1,
.reg_shift = 2,
.clock = V_NS16550_CLK
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(omap3logic_uart) = {
......
......@@ -47,7 +47,8 @@ static const u32 gpmc_lab_enet[] = {
static const struct ns16550_platdata zoom1_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(zoom1_uart) = {
......
......@@ -70,7 +70,8 @@ static struct {
static const struct ns16550_platdata overo_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(overo_uart) = {
......
......@@ -93,7 +93,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
static const struct ns16550_platdata cairo_serial = {
.base = OMAP34XX_UART2,
.reg_shift = 2,
.clock = V_NS16550_CLK
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(cairo_uart) = {
......
......@@ -75,7 +75,8 @@ static struct {
static const struct ns16550_platdata beagle_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(beagle_uart) = {
......
......@@ -48,7 +48,8 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
static const struct ns16550_platdata devkit8000_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(devkit8000_uart) = {
......
......@@ -20,9 +20,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
#define UART_MCRVAL (UART_MCR_DTR | \
UART_MCR_RTS) /* RTS/DTR */
#define UART_FCRVAL (UART_FCR_FIFO_EN | \
UART_FCR_RXSR | \
UART_FCR_TXSR) /* Clear & enable FIFOs */
#ifndef CONFIG_DM_SERIAL
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
......@@ -138,7 +135,7 @@ static u32 ns16550_getfcr(NS16550_t port)
#else
static u32 ns16550_getfcr(NS16550_t port)
{
return UART_FCRVAL;
return UART_FCR_DEFVAL;
}
#endif
......@@ -275,7 +272,7 @@ static inline void _debug_uart_init(void)
CONFIG_BAUDRATE);
serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
serial_dout(&com_port->mcr, UART_MCRVAL);
serial_dout(&com_port->fcr, UART_FCRVAL);
serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
serial_dout(&com_port->dll, baud_divisor & 0xff);
......@@ -440,7 +437,7 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
return -EINVAL;
}
plat->fcr = UART_FCRVAL;
plat->fcr = UART_FCR_DEFVAL;
if (port_type == PORT_JZ4780)
plat->fcr |= UART_FCR_UME;
......
......@@ -27,6 +27,7 @@ static int rockchip_serial_probe(struct udevice *dev)
plat->plat.base = plat->dtplat.reg[0];
plat->plat.reg_shift = plat->dtplat.reg_shift;
plat->plat.clock = plat->dtplat.clock_frequency;
plat->plat.fcr = UART_FCR_DEFVAL;
dev->platdata = &plat->plat;
return ns16550_serial_probe(dev);
......
......@@ -121,6 +121,11 @@ typedef struct NS16550 *NS16550_t;
/* Ingenic JZ47xx specific UART-enable bit. */
#define UART_FCR_UME 0x10
/* Clear & enable FIFOs */
#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
UART_FCR_RXSR | \
UART_FCR_TXSR)
/*
* These are the definitions for the Modem Control Register
*/
......
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