emcraft_som : add the emcraft code to the latest imx8 u-boot for SPL SDP

parent 8be98e93
......@@ -54,6 +54,42 @@ config TARGET_IMX8MM_EVK
endchoice
choice
prompt "EmCraft i.MX8M board select"
optional
config TARGET_EMCRAFT_IMX8M_SOM
bool "emcraft_imx8m_som"
select IMX8M
select IMX8MQ
select SUPPORT_SPL
config TARGET_EMCRAFT_IMX8M_LPDDR4_SOM
bool "emcraft_imx8m_lpddr4_som"
select IMX8M
select IMX8MQ
select SUPPORT_SPL
config TARGET_EMCRAFT_IMX8M_LPDDR4_2GB_SOM
bool "emcraft_imx8m_lpddr4_2gb_som"
select IMX8M
select IMX8MQ
select SUPPORT_SPL
config TARGET_EMCRAFT_IMX8M_LPDDR4_3GB_SOM
bool "emcraft_imx8m_lpddr4_3gb_som"
select IMX8M
select IMX8MQ
select SUPPORT_SPL
config TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM
bool "emcraft_imx8m_lpddr4_800mhz_2gb_som"
select IMX8M
select IMX8MQ
select SUPPORT_SPL
endchoice
config SYS_SOC
default "imx8m"
......@@ -62,5 +98,6 @@ source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mq_arm2/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mm_val/Kconfig"
source "board/emcraft/imx8m_som/Kconfig"
endif
......@@ -391,7 +391,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
fsl-imx8mq-phanbell.dtb \
fsl-imx8mq-ddr4-arm2.dtb \
fsl-imx8mm-ddr4-val.dtb \
fsl-imx8mm-evk.dtb
fsl-imx8mm-evk.dtb \
emcraft-imx8m-som.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-lpddr4-arm2.dtb \
fsl-imx8qm-ddr4-arm2.dtb \
......
This diff is collapsed.
../freescale/common
\ No newline at end of file
config SYS_BOARD
default "imx8m_som"
config SYS_VENDOR
default "emcraft"
config SYS_CONFIG_NAME
default "imx8m_som"
#
# Copyright 2016 Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8m_som.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
#obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o
ifdef CONFIG_TARGET_EMCRAFT_IMX8M_SOM
obj-y += ddr/ddr3l/ddr3_phyinit_train_1600mts_x16_ret.o \
ddr/ddr3l/ddr3_pmu_training_1600mts_x16_ret.o \
ddr/ddr3l/dram_pll_cfg.o ddr/ddr3l/helper.o
else
ifdef CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_2GB_SOM
obj-y += ddr/lpddr4_2gb/ddr_init.o ddr/lpddr4_2gb/ddrphy_train.o \
ddr/lpddr4/helper.o
else ifdef CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_3GB_SOM
obj-y += ddr/lpddr4_3gb/ddr_init.o ddr/lpddr4_3gb/ddrphy_train.o \
ddr/lpddr4/helper.o
else ifdef CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM
obj-y += ddr/lpddr4_800mhz_2gb/ddr_init.o ddr/lpddr4_800mhz_2gb/ddrphy_train.o \
ddr/lpddr4/helper.o
else
obj-y += ddr/lpddr4/ddr_init.o ddr/lpddr4/ddrphy_train.o \
ddr/lpddr4/helper.o
endif
endif
endif
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef SRC_DDRC_RCR_ADDR
#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
#endif
#ifndef DDR_CSD1_BASE_ADDR
#define DDR_CSD1_BASE_ADDR 0x40000000
#endif
enum fw_type {
FW_1D_IMAGE,
FW_2D_IMAGE,
};
void ddr_init(void);
void ddr_load_train_code(enum fw_type type);
void wait_ddrphy_training_complete(void);
void ddr3_phyinit_train_1600mts(void);
void ddr4_phyinit_train_2400mts(void);
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);
}
static inline uint32_t reg32_read(unsigned long addr)
{
return readl(addr);
}
/*
static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
{
writel(val, addr);
}
*/
static inline void reg32setbit(unsigned long addr, u32 bit)
{
setbits_le32(addr, (1 << bit));
}
static inline void reg32clrbit(unsigned long addr, u32 bit)
{
clrbits_le32(addr, (1 << bit));
}
/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ddr_h__
#define __ddr_h__
#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
#define ddr_printf(args...) printf(args)
#else
#define ddr_printf(args...)
#endif
#define DPRINTF_L0 ddr_printf
#define DPRINTF_L2 ddr_printf
#define printk ddr_printf
typedef unsigned int WORD;
#define printk printf
#define info_trigger
#define reg32_write(a,v) writel(v,a)
#define reg32_read(v) readl(v)
#define reg32setbit(addr,bitpos) \
reg32_write((addr),(reg32_read((addr)) | (1<<(bitpos))))
#define reg16setbit(addr,bitpos) \
reg16_write((addr),(reg16_read((addr)) | (1<<(bitpos))))
#define reg8setbit(addr,bitpos) \
reg8_write((addr),(reg16_read((addr)) | (1<<(bitpos))))
#define reg32clrbit(addr,bitpos) \
reg32_write((addr),(reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos)))))
#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr), data)
#define dwc_ddrphy_apb_rd(addr) reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr))
enum fw_type {
FW_1D_IMAGE,
FW_2D_IMAGE,
};
void ddr_load_train_code(enum fw_type type);
void lpddr4_800M_cfg_phy(void);
//#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
//#define DDR_CSD1_BASE_ADDR 0x40000000
#define ANAMIX_PLL_BASE_ADDR 0x30360000
#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
#define GPC_PU_PWRHSK 0x303A01FC
#define GPC_TOP_CONFIG_OFFSET 0x0000
#define AIPS1_ARB_BASE_ADDR 0x30000000
#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define AIPS1_OFF_BASE_ADDR AIPS_TZ1_BASE_ADDR+0x200000
#define GPC_IPS_BASE_ADDR AIPS1_OFF_BASE_ADDR+0x1A0000
#define GPC_BASE_ADDR GPC_IPS_BASE_ADDR
#define GPC_PU_PWRHSK (GPC_BASE_ADDR + GPC_TOP_CONFIG_OFFSET + 0x01FC) //added by baoxye
#define CCM_IPS_BASE_ADDR AIPS1_OFF_BASE_ADDR+0x180000
#define CCM_SRC_CTRL_OFFSET CCM_IPS_BASE_ADDR+0x800
#define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET+0x10*n)
extern void mem_test(u32 type);
void inline sscgpll_bypass_enable(WORD reg_addr) {
WORD read_data;
read_data = reg32_read(reg_addr);
reg32_write(reg_addr, read_data | 0x00000010);
read_data = reg32_read(reg_addr);
reg32_write(reg_addr, read_data | 0x00000020);
}
void inline sscgpll_bypass_disable(WORD reg_addr) {
WORD read_data;
read_data = reg32_read(reg_addr);
reg32_write(reg_addr, read_data & 0xffffffdf);
read_data = reg32_read(reg_addr);
reg32_write(reg_addr, read_data & 0xffffffef);
}
unsigned int inline wait_pll_lock(WORD reg_addr) {
WORD pll_lock;
pll_lock = reg32_read(reg_addr) >> 31;
return pll_lock;
}
#endif
/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr_memory_map.h>
#include <asm/arch/clock.h>
#include "ddr3.h"
#define RUN_ON_SILICON
#define SAVE_DDRPHY_TRAIN_ADDR 0x00916000
#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
#define DDR_CSD1_BASE_ADDR 0x40000000
#define DDR_CSD2_BASE_ADDR 0x80000000
#define GPC_PU_PWRHSK 0x303A01FC
#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr), data)
#define dwc_ddrphy_apb_rd(addr) (reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*(addr)))
//#define DDR_DEBUG
//#include "restore_1d2d_trained_csr_ddr3_p0.c"
//#include "save_1d2d_trained_csr_ddr3_p0.c"
//#include "dram_pll_cfg.c"
//#include "ddr3_phyinit_task.c"
//#include "ddr3_phyinit_train_1600mts_x16_ret.c"
void umctl2_cfg(){
unsigned int tmp;
reg32_write(DDRC_DBG1(0), 0x00000001);
reg32_write(DDRC_PWRCTL(0), 0x00000001);
do{
tmp = 0x7 & (reg32_read(DDRC_STAT(0)));
}while(tmp);// wait init state
//reg32_write(DDRC_MSTR(0), 0x83040001); // [0]ddr3, [x:24]=1--1 rank, [19:16]=4--BL-8, [29]frequency_mode=1
reg32_write(DDRC_MSTR(0), 0x81041001); //kanzi x16: [0]ddr3, [x:24]=1--1 rank, [19:16]=4--BL-8, [29]frequency_mode=1, [13:12]data_bus_width=1
//reg32_write(DDRC_MSTR(0), 0x83040001);
reg32_write(DDRC_MRCTRL0(0), 0x40004030);
reg32_write(DDRC_MRCTRL1(0), 0x0001c68e);
reg32_write(DDRC_MRCTRL2(0), 0x921b7e95);
reg32_write(DDRC_DERATEEN(0), 0x00000506);
reg32_write(DDRC_DERATEINT(0), 0x9a4fbdf1);
reg32_write(DDRC_MSTR2(0), 0x00000001);
reg32_write(DDRC_PWRCTL(0), 0x000000a8);
reg32_write(DDRC_PWRTMG(0), 0x00532203);
reg32_write(DDRC_HWLPCTL(0), 0x0b6d0000);
reg32_write(DDRC_HWFFCCTL(0), 0x00000030);
reg32_write(DDRC_RFSHCTL0(0), 0x00203020);
reg32_write(DDRC_RFSHCTL1(0), 0x0001000d);
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
reg32_write(DDRC_RFSHTMG(0), 0x0061008c);
reg32_write(DDRC_CRCPARCTL0(0), 0x00000000);
reg32_write(DDRC_CRCPARCTL1(0), 0x00000000);
reg32_write(DDRC_INIT0(0), 0xc0030002);
reg32_write(DDRC_INIT1(0), 0x0001000b);
reg32_write(DDRC_INIT2(0), 0x00006303);
reg32_write(DDRC_INIT3(0), 0x0d700044);//MR1, MR0
reg32_write(DDRC_INIT4(0), 0x00180000);//MR2
reg32_write(DDRC_INIT5(0), 0x00090071);
reg32_write(DDRC_INIT6(0), 0x00000000);
reg32_write(DDRC_INIT7(0), 0x00000000);
reg32_write(DDRC_DIMMCTL(0), 0x00000032); //[1] dimm_addr_mirr_en, it will effect the MRS if use umctl2 to initi dram.
reg32_write(DDRC_RANKCTL(0), 0x00000ee5);
reg32_write(DDRC_DRAMTMG0(0), 0x0c101a0e);
reg32_write(DDRC_DRAMTMG1(0), 0x000a0314);
reg32_write(DDRC_DRAMTMG2(0), 0x04060509);
reg32_write(DDRC_DRAMTMG3(0), 0x00002006);
reg32_write(DDRC_DRAMTMG4(0), 0x06020306);
reg32_write(DDRC_DRAMTMG5(0), 0x0b060202);
reg32_write(DDRC_DRAMTMG6(0), 0x060a0009);
reg32_write(DDRC_DRAMTMG7(0), 0x0000060b);
reg32_write(DDRC_DRAMTMG8(0), 0x01017c0a);
reg32_write(DDRC_DRAMTMG9(0), 0x4000000e);
reg32_write(DDRC_DRAMTMG10(0), 0x00070803);
reg32_write(DDRC_DRAMTMG11(0), 0x0101000b);
reg32_write(DDRC_DRAMTMG12(0), 0x00000000);
reg32_write(DDRC_DRAMTMG13(0), 0x5d000000);
reg32_write(DDRC_DRAMTMG14(0), 0x00000b39);
reg32_write(DDRC_DRAMTMG15(0), 0x80000000);
reg32_write(DDRC_DRAMTMG17(0), 0x00f1006a);
reg32_write(DDRC_ZQCTL0(0), 0x50800020);
reg32_write(DDRC_ZQCTL1(0), 0x00000070);
reg32_write(DDRC_ZQCTL2(0), 0x00000000);
reg32_write(DDRC_DFITMG0(0), 0x03868203);
reg32_write(DDRC_DFITMG1(0), 0x00020103);
reg32_write(DDRC_DFILPCFG0(0), 0x07713121);
reg32_write(DDRC_DFILPCFG1(0), 0x00000010);
reg32_write(DDRC_DFIUPD0(0), 0xe0400018);
reg32_write(DDRC_DFIUPD1(0), 0x0005003c);
reg32_write(DDRC_DFIUPD2(0), 0x80000000);
reg32_write(DDRC_DFIMISC(0), 0x00000011);
reg32_write(DDRC_DFITMG2(0), 0x00000603);
reg32_write(DDRC_DFITMG3(0), 0x00000001);
reg32_write(DDRC_DBICTL(0), 0x00000001);
reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000);
//row15,bank3,clo10
reg32_write(DDRC_ADDRMAP0(0), 0x00000015); //[4:0] cs-bit0: axi[27]
reg32_write(DDRC_ADDRMAP1(0), 0x00070707);
reg32_write(DDRC_ADDRMAP2(0), 0x00000000);
reg32_write(DDRC_ADDRMAP3(0), 0x00000000);
reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f);
reg32_write(DDRC_ADDRMAP5(0), 0x06060606);
reg32_write(DDRC_ADDRMAP6(0), 0x0f060606);
reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f);
reg32_write(DDRC_ADDRMAP8(0), 0x00000000);
reg32_write(DDRC_ODTCFG(0), 0x0600060c);
reg32_write(DDRC_ODTMAP(0), 0x00000001);
reg32_write(DDRC_DBG0(0), 0x00000017);
reg32_write(DDRC_DBG1(0), 0x00000000);
reg32_write(DDRC_DBGCMD(0), 0x00000000);
reg32_write(DDRC_SWCTL(0), 0x00000001);
}
//void TEST_NAME()
void ddr3_pub_train_1600mts_ret_16bit_1rank()
{
volatile unsigned int tmp, tmp_t, i;
//verilog_trigger(vt_event1);
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000003);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
//change the clock source of dram_apb_clk_root
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16)); //to source 4 --800MHz/4
//disable the phy iso
reg32_write(0x303A00EC,0x0000ffff); //PGC_CPU_MAPPING
reg32setbit(0x303A00F8,5);//PU_PGC_SW_PUP_REQ
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
DDR_PLL_CONFIG_400MHz();
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
// RESET: <core_ddrc_rstn> ASSERTED (ACTIVE LOW)
// RESET: <presetn> ASSERTED (ACTIVE LOW)
// RESET: <aresetn> for Port 0 ASSERTED (ACTIVE LOW)
// RESET: <presetn> DEASSERTED
umctl2_cfg();
reg32setbit(DDRC_RFSHCTL3(0),0);//dis_auto_refresh
//RESET: <ctn> DEASSERTED
//RESET: <a Port 0 DEASSERTED(0)
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); // release all reset
reg32_write(DDRC_DBG1(0), 0x00000000); // ('b00000000_00000000_00000000_00000000) ('d0)
reg32setbit(DDRC_PWRCTL(0),5);//selfref_sw=1, self-refresh
reg32clrbit(DDRC_SWCTL(0), 0);//sw_done=0, enable quasi-dynamic programming
reg32_write(DDRC_DFIMISC(0), 0x00000000);
ddr_printf("vt_event5\n");
ddr3_phyinit_train_1600mts_x16_ret(0);//before retention
do {
tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00020097);
ddr_printf("C: Wait CalBusy = 0\n");
}while(tmp != 0);
reg32setbit(DDRC_DFIMISC(0),5);//dfi_init_start=1
do{
tmp=0x1 & (reg32_read(DDRC_DFISTAT(0)));
}while(!tmp);// wait DFISTAT.dfi_init_complete to 1
reg32clrbit(DDRC_DFIMISC(0),5);//dfi_init_start=0
reg32setbit(DDRC_DFIMISC(0),0);//dfi_init_complete_en=1
reg32clrbit(DDRC_PWRCTL(0),5);//selfref_sw=0, exit self-refresh
reg32setbit(DDRC_SWCTL(0), 0);//sw_done=1, disable quasi-dynamic programming
//wait SWSTAT.sw_done_ack to 1
do{
tmp=0x1 & (reg32_read(DDRC_SWSTAT(0)));
}while(!tmp);
//wait STAT to normal state
do{
tmp=0x7 & (reg32_read(DDRC_STAT(0)));
}while(tmp != 0x1);
reg32_write(DDRC_PCTRL_0(0), 0x00000001); //enable port 0
reg32clrbit(DDRC_RFSHCTL3(0), 0); // auto-refresh enable
#if 0
for (i=32; i<40; i++){
mem32_write(DDR_CSD1_BASE_ADDR+i*4, i);
}
for (i=32; i<40; i++){
tmp=mem32_read(DDR_CSD1_BASE_ADDR+i*4);
if(tmp!=i) {verilog_trigger(vt_fail);
info_trigger(i,tmp,0);
}
}
verilog_trigger(vt_pass);
DPRINTF_L0("DDR memory only write test via memcpy\n");
//while(1)
{//only write DDR memory
for(i=0;i<0x1000;i++){//0x2000:1GB
memcpy((DDR_MEM_RANK0_START_ADDR+i*0x20000),0x007e0000,0x00020000);//target/source/len//rank0
}
//DPRINTF_L2(".");
}
DPRINTF_L0("DDR memory read&write test via memcpy\n");
while(1){//read/write DDR memory
DPRINTF_L2("*");
memcpy(DDR_MEM_RANK0_START_ADDR,(DDR_MEM_RANK0_START_ADDR+0x0),0x10000000);//target/source/len//512MB//rank0
DPRINTF_L0("test result=0x%lx\r\n",memcmp(DDR_MEM_RANK0_START_ADDR,(DDR_MEM_RANK0_START_ADDR+0x0),0x10000000));
}
#endif
//mem_test(0);
}
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr_memory_map.h>
#include <asm/arch/clock.h>
#include "../ddr.h"
#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
#define ddr_printf(args...) printf(args)
#else
#define ddr_printf(args...)
#endif
#include "../wait_ddrphy_training_complete.c"
volatile unsigned int tmp;
void umctl2_cfg(void){
reg32_write(DDRC_DBG1(0), 0x00000001);
reg32_write(DDRC_PWRCTL(0), 0x00000001);
do{
tmp = 0x7 & (reg32_read(DDRC_STAT(0)));
} while (tmp);/* wait init state */
reg32_write(DDRC_MSTR(0), 0x83040001);/* two rank */
reg32_write(DDRC_MRCTRL0(0), 0x40004030);
reg32_write(DDRC_MRCTRL1(0), 0x0001c68e);
reg32_write(DDRC_MRCTRL2(0), 0x921b7e95);
reg32_write(DDRC_DERATEEN(0), 0x00000506);
reg32_write(DDRC_DERATEINT(0), 0x9a4fbdf1);
reg32_write(DDRC_MSTR2(0), 0x00000001);
reg32_write(DDRC_PWRCTL(0), 0x000000a8);
reg32_write(DDRC_PWRTMG(0), 0x00532203);
reg32_write(DDRC_HWLPCTL(0), 0x0b6d0000);
reg32_write(DDRC_HWFFCCTL(0), 0x00000030);
reg32_write(DDRC_RFSHCTL0(0), 0x00203020);
reg32_write(DDRC_RFSHCTL1(0), 0x0001000d);
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
reg32_write(DDRC_RFSHTMG(0), 0x0061008c);
reg32_write(DDRC_CRCPARCTL0(0), 0x00000000);
reg32_write(DDRC_CRCPARCTL1(0), 0x00000000);
reg32_write(DDRC_INIT0(0), 0xc0030002);
reg32_write(DDRC_INIT1(0), 0x0001000b);
reg32_write(DDRC_INIT2(0), 0x00006303);
reg32_write(DDRC_INIT3(0), 0x0d700044);/* MR1, MR0 */
reg32_write(DDRC_INIT4(0), 0x00180000);/* MR2 */
reg32_write(DDRC_INIT5(0), 0x00090071);
reg32_write(DDRC_INIT6(0), 0x00000000);
reg32_write(DDRC_INIT7(0), 0x00000000);
reg32_write(DDRC_DIMMCTL(0), 0x00000032);
reg32_write(DDRC_RANKCTL(0), 0x00000ee5);
reg32_write(DDRC_DRAMTMG0(0), 0x0c101a0e);
reg32_write(DDRC_DRAMTMG1(0), 0x000a0314);
reg32_write(DDRC_DRAMTMG2(0), 0x04060509);
reg32_write(DDRC_DRAMTMG3(0), 0x00002006);
reg32_write(DDRC_DRAMTMG4(0), 0x06020306);
reg32_write(DDRC_DRAMTMG5(0), 0x0b060202);
reg32_write(DDRC_DRAMTMG6(0), 0x060a0009);
reg32_write(DDRC_DRAMTMG7(0), 0x0000060b);
reg32_write(DDRC_DRAMTMG8(0), 0x01017c0a);
reg32_write(DDRC_DRAMTMG9(0), 0x4000000e);
reg32_write(DDRC_DRAMTMG10(0), 0x00070803);
reg32_write(DDRC_DRAMTMG11(0), 0x0101000b);
reg32_write(DDRC_DRAMTMG12(0), 0x00000000);
reg32_write(DDRC_DRAMTMG13(0), 0x5d000000);
reg32_write(DDRC_DRAMTMG14(0), 0x00000b39);
reg32_write(DDRC_DRAMTMG15(0), 0x80000000);
reg32_write(DDRC_DRAMTMG17(0), 0x00f1006a);
reg32_write(DDRC_ZQCTL0(0), 0x50800020);
reg32_write(DDRC_ZQCTL1(0), 0x00000070);
reg32_write(DDRC_ZQCTL2(0), 0x00000000);
reg32_write(DDRC_DFITMG0(0), 0x03868203);
reg32_write(DDRC_DFITMG1(0), 0x00020103);
reg32_write(DDRC_DFILPCFG0(0), 0x07713121);
reg32_write(DDRC_DFILPCFG1(0), 0x00000010);
reg32_write(DDRC_DFIUPD0(0), 0xe0400018);
reg32_write(DDRC_DFIUPD1(0), 0x0005003c);
reg32_write(DDRC_DFIUPD2(0), 0x00000000);
reg32_write(DDRC_DFIMISC(0), 0x00000011);
reg32_write(DDRC_DFITMG2(0), 0x00000603);
reg32_write(DDRC_DFITMG3(0), 0x00000001);
reg32_write(DDRC_DBICTL(0), 0x00000001);
reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000);
reg32_write(DDRC_ADDRMAP0(0), 0x00000016); /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */
reg32_write(DDRC_ADDRMAP1(0), 0x00080808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */
reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2; [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */
reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6; [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */
reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */
reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6; [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */
reg32_write(DDRC_ADDRMAP6(0), 0x0f070707); /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */
reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f);
reg32_write(DDRC_ADDRMAP8(0), 0x00000000); /* [5:0] bg-b0; [13:8]bg-b1 */
reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
reg32_write(DDRC_ADDRMAP11(0), 0x00000000);
reg32_write(DDRC_ODTCFG(0), 0x041d0f5c);
reg32_write(DDRC_ODTMAP(0), 0x00000201);
reg32_write(DDRC_SCHED(0), 0x7ab50b07);
reg32_write(DDRC_SCHED1(0), 0x00000022);
reg32_write(DDRC_PERFHPR1(0), 0x7b00665e);
reg32_write(DDRC_PERFLPR1(0), 0x2b00c4e1);
reg32_write(DDRC_PERFWR1(0), 0xb700c9fe);
reg32_write(DDRC_DBG0(0), 0x00000017);
reg32_write(DDRC_DBG1(0), 0x00000000);
reg32_write(DDRC_DBGCMD(0), 0x00000000);
reg32_write(DDRC_SWCTL(0), 0x00000001);
reg32_write(DDRC_POISONCFG(0), 0x00010000);
reg32_write(DDRC_PCCFG(0), 0x00000100);
reg32_write(DDRC_PCFGR_0(0), 0x00003051);
reg32_write(DDRC_PCFGW_0(0), 0x000061d2);
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
reg32_write(DDRC_PCFGQOS0_0(0), 0x02100b04);
reg32_write(DDRC_PCFGQOS1_0(0), 0x003f0353);
reg32_write(DDRC_PCFGWQOS0_0(0), 0x00000002);
reg32_write(DDRC_PCFGWQOS1_0(0), 0x000005fd);
}
void ddr_init(void)
{
/* change the clock source of dram_apb_clk_root */
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16));
/* disable the clock gating */
reg32_write(0x303A00EC,0x0000ffff);
reg32setbit(0x303A00F8,5);
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
dram_pll_init(SSCG_PLL_OUT_400M);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
/* Configure uMCTL2's registers */
umctl2_cfg();
reg32setbit(DDRC_RFSHCTL3(0),0); /* dis_auto_refresh */
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
ddr_load_train_code(FW_1D_IMAGE);
reg32_write(DDRC_DBG1(0), 0x00000000); /* ('b00000000_00000000_00000000_00000000) ('d0) */
reg32setbit(DDRC_PWRCTL(0),5); /* selfref_sw=1, self-refresh */
reg32clrbit(DDRC_SWCTL(0), 0); /* sw_done=0, enable quasi-dynamic programming */
reg32_write(DDRC_DFIMISC(0), 0x00000000);
/* Configure DDR3L PHY's registers */
ddr3_phyinit_train_1600mts();
do {
tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00020097);
} while (tmp != 0);
reg32setbit(DDRC_DFIMISC(0),5);/* dfi_init_start=1 */
do{
tmp = 0x1 & (reg32_read(DDRC_DFISTAT(0)));
} while (!tmp);/* wait DFISTAT.dfi_init_complete to 1 */
reg32clrbit(DDRC_DFIMISC(0),5);/* dfi_init_start=0 */
reg32setbit(DDRC_DFIMISC(0),0);/* dfi_init_complete_en=1 */
reg32clrbit(DDRC_PWRCTL(0),5);/* selfref_sw=0, exit self-refresh */
reg32setbit(DDRC_SWCTL(0), 0);/* sw_done=1, disable quasi-dynamic programming */
/* wait SWSTAT.sw_done_ack to 1 */
do{
tmp = 0x1 & (reg32_read(DDRC_SWSTAT(0)));
} while (!tmp);
/* wait STAT to normal state */
do{
tmp = 0x7 & (reg32_read(DDRC_STAT(0)));
} while (tmp != 0x1);
reg32_write(DDRC_PCTRL_0(0), 0x00000001); /* enable port 0 */
reg32clrbit(DDRC_RFSHCTL3(0), 0); /* auto-refresh enable */
}
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/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "config.h"
#ifdef DDR3_1600MHZ_RET_16BIT_1RANK_FW09
#include "soc_api.h"
#include "ddr_memory_map.h"
#define printf DPRINTF_L0
void DDR_PLL_CONFIG_266MHz(void) {
WORD ddr_pll_lock;
sscgpll_bypass_enable(HW_DRAM_PLL_CFG0_ADDR