Commit 3365b4eb authored by Masahiro Yamada's avatar Masahiro Yamada

ARM: UniPhier: add PH1-sLD3 SoC support

The init code for UMC (Unified Memory Controller) and PLL has not
been mainlined yet, but U-boot proper should work.
Signed-off-by: 's avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent ad6670ee
......@@ -10,13 +10,17 @@ choice
prompt "UniPhier SoC select"
default MACH_PH1_PRO4
config MACH_PH1_PRO4
bool "PH1-Pro4"
config MACH_PH1_SLD3
bool "PH1-sLD3"
select UNIPHIER_SMP
config MACH_PH1_LD4
bool "PH1-LD4"
config MACH_PH1_PRO4
bool "PH1-Pro4"
select UNIPHIER_SMP
config MACH_PH1_SLD8
bool "PH1-sLD8"
......@@ -64,11 +68,11 @@ choice
config DDR_FREQ_1600
bool "DDR3 1600"
depends on MACH_PH1_PRO4 || MACH_PH1_LD4
depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_PRO4
config DDR_FREQ_1333
bool "DDR3 1333"
depends on MACH_PH1_LD4 || MACH_PH1_SLD8
depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_SLD8
endchoice
......
......@@ -32,6 +32,7 @@ obj-y += timer.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/
obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
/*
* UniPhier SC (System Control) block registers
*
* Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -9,7 +9,11 @@
#ifndef ARCH_SC_REGS_H
#define ARCH_SC_REGS_H
#if defined(CONFIG_MACH_PH1_SLD3)
#define SC_BASE_ADDR 0xf1840000
#else
#define SC_BASE_ADDR 0x61840000
#endif
#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
......
......@@ -55,11 +55,12 @@
#if defined(CONFIG_MACH_PH1_PRO4)
# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
#elif defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
defined(CONFIG_MACH_PH1_SLD8)
# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
#endif
#if defined(CONFIG_MACH_PH1_PRO4)
#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_PRO4)
#define SG_PINSELBITS 4
#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
#define SG_PINSELBITS 8
......
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \
early_pinctrl.o pll_spectrum.o umc_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
obj-$(CONFIG_SPL_DM) += platdevice.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
endif
obj-y += boot-mode.o
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/bcu-regs.h>
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
void bcu_init(void)
{
int shift;
writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
/*
* 0xe0000000-0xefffffff: Ex-bus
* 0xf0000000-0xfbffffff: ASM bus
* 0xfc000000-0xffffffff: OCM bus
*/
writel(0x24440000, BCSCR5);
/* Specify DDR channel */
shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;
writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
shift -= 32;
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
}
/*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <linux/io.h>
#include <mach/boot-device.h>
#include <mach/sg-regs.h>
#include <mach/sbc-regs.h>
struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "External Master"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{ /* sentinel */ }
};
int get_boot_mode_sel(void)
{
return readl(SG_PINMON0) & 0x3f;
}
u32 spl_boot_device(void)
{
int boot_mode;
if (boot_is_swapped())
return BOOT_DEVICE_NOR;
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
}
#include "../ph1-pro4/clkrst_init.c"
#include "../ph1-pro4/early_clkrst_init.c"
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <mach/sg-regs.h>
void early_pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(63, 0); /* RXD0 */
sg_set_pinsel(64, 1); /* TXD0 */
sg_set_pinsel(65, 0); /* RXD1 */
sg_set_pinsel(66, 1); /* TXD1 */
sg_set_pinsel(96, 2); /* RXD2 */
sg_set_pinsel(102, 2); /* TXD2 */
#endif
}
/*
* On-chip UART initializaion for low-level debugging
*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
#include <mach/bcu-regs.h>
#include <mach/sc-regs.h>
#include <mach/sg-regs.h>
#include <mach/debug-uart.S>
ENTRY(setup_lowlevel_debug)
ldr r0, =BCSCR5
ldr r1, =0x24440000
str r1, [r0]
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
init_debug_uart r0, r1, r2
set_pinsel 63, 0, r0, r1
set_pinsel 64, 1, r0, r1
mov pc, lr
ENDPROC(setup_lowlevel_debug)
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/types.h>
#include <linux/sizes.h>
#include <mach/sg-regs.h>
static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
{
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case SZ_64M:
ret = SG_MEMCONF_CH2_SZ_64M;
break;
case SZ_128M:
ret = SG_MEMCONF_CH2_SZ_128M;
break;
case SZ_256M:
ret = SG_MEMCONF_CH2_SZ_256M;
break;
case SZ_512M:
ret = SG_MEMCONF_CH2_SZ_512M;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH2_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH2_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
u32 memconf_additional_val(void)
{
return sg_memconf_val_ch2(CONFIG_SDRAM2_SIZE, CONFIG_DDR_NUM_CH2);
}
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <mach/sg-regs.h>
void pin_init(void)
{
#ifdef CONFIG_USB_EHCI_UNIPHIER
sg_set_pinsel(13, 0); /* USB0OC */
sg_set_pinsel(14, 1); /* USB0VBUS */
sg_set_pinsel(15, 0); /* USB1OC */
sg_set_pinsel(16, 1); /* USB1VBUS */
sg_set_pinsel(17, 0); /* USB2OC */
sg_set_pinsel(18, 1); /* USB2VBUS */
sg_set_pinsel(19, 0); /* USB3OC */
sg_set_pinsel(20, 1); /* USB3VBUS */
#endif
}
#include "../ph1-ld4/platdevice.c"
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
void pll_init(void)
{
/* add pll init code here */
}
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sc-regs.h>
void enable_dpll_ssc(void)
{
u32 tmp;
tmp = readl(SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
writel(tmp, SC_DPLLCTRL);
}
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
/* only address/data multiplex mode is supported */
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
*/
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
*
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
* 0x00000000-0x01ffffff: mask ROM
* 0x02000000-0x03efffff: memory bank (31MB)
* 0x03f00000-0x03ffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
}
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
/* only address/data multiplex mode is supported */
/* XECS0 : boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02);
/* XECS1 : sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
/* XECS2 : peripherals */
writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20);
writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21);
writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22);
/* base address regsiters */
writel(0x0000bc01, SBBASE0);
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE2);
sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
}
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
void sg_init(void)
{
}
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
int umc_init(void)
{
/* add UMC init code here */
printf("Implement memory init code\n");
return 0;
}
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_MACH_PH1_SLD3=y
CONFIG_PFC_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
......@@ -28,14 +28,18 @@ Tested toolchains
Compile the source
------------------
PH1-Pro4:
$ make ph1_pro4_defconfig
PH1-sLD3:
$ make ph1_sld3_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
PH1-LD4:
$ make ph1_ld4_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
PH1-Pro4:
$ make ph1_pro4_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
PH1-sLD8:
$ make ph1_sld8_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
......
......@@ -9,15 +9,18 @@
#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__
#if defined(CONFIG_MACH_PH1_PRO4)
#if defined(CONFIG_MACH_PH1_SLD3)
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 2
#define CONFIG_DDR_NUM_CH1 1
#define CONFIG_DDR_NUM_CH2 1
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x20000000
#define CONFIG_SDRAM1_BASE 0xa0000000
#define CONFIG_SDRAM1_BASE 0xc0000000
#define CONFIG_SDRAM1_SIZE 0x20000000
#define CONFIG_SDRAM2_BASE 0xc0000000
#define CONFIG_SDRAM2_SIZE 0x10000000
#endif
#if defined(CONFIG_MACH_PH1_LD4)
......@@ -31,6 +34,17 @@
#define CONFIG_SDRAM1_SIZE 0x10000000
#endif
#if defined(CONFIG_MACH_PH1_PRO4)
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 2
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x20000000
#define CONFIG_SDRAM1_BASE 0xa0000000
#define CONFIG_SDRAM1_SIZE 0x20000000
#endif
#if defined(CONFIG_MACH_PH1_SLD8)
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
......@@ -177,8 +191,13 @@
#define CONFIG_NAND_DENALI_ECC_SIZE 1024
#ifdef CONFIG_MACH_PH1_SLD3
#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
#else
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
#endif
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
......@@ -294,7 +313,8 @@
#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
#endif
#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
defined(CONFIG_MACH_PH1_SLD8)
#define CONFIG_SPL_TEXT_BASE 0x00040000
#endif
#if defined(CONFIG_MACH_PH1_PRO4)
......
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