Commit 3599774e authored by Roger Quadros's avatar Roger Quadros Committed by Tom Rini

dra7xx: Enable USB_PHY3 32KHz clock

DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.
Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
parent 55efadde
......@@ -614,9 +614,14 @@ void enable_usb_clocks(int index)
setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Enable 32 KHz clock for dwc3 */
/* Enable 32 KHz clock for USB_PHY1 */
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Enable 32 KHz clock for USB_PHY3 */
if (is_dra7xx())
setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
......@@ -664,9 +669,14 @@ void disable_usb_clocks(int index)
clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Disable 32 KHz clock for dwc3 */
/* Disable 32 KHz clock for USB_PHY1 */
clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Disable 32 KHz clock for USB_PHY3 */
if (is_dra7xx())
clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
......
......@@ -820,6 +820,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_clkmode_dpll_gmac = 0x4a0052a8,
.cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
.cm_coreaon_usb_phy3_core_clkctrl = 0x4a008698,
.cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0,
/* cm1.mpu */
......
......@@ -145,6 +145,7 @@ struct prcm_regs {
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
u32 cm_coreaon_usb_phy3_core_clkctrl;
u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */
......
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