Commit 37228621 authored by Paul Burton's avatar Paul Burton Committed by Daniel Schwierzeck

MIPS: Split I & D cache line size config

Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: default avatarDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
parent ace3be4f
......@@ -252,21 +252,27 @@ config SYS_DCACHE_SIZE
help
The total size of the L1 Dcache, if known at compile time.
config SYS_DCACHE_LINE_SIZE
hex
default 0
help
The size of L1 Dcache lines, if known at compile time.
config SYS_ICACHE_SIZE
int
default 0
help
The total size of the L1 ICache, if known at compile time.
config SYS_CACHELINE_SIZE
config SYS_ICACHE_LINE_SIZE
int
default 0
help
The size of L1 cache lines, if known at compile time.
The size of L1 Icache lines, if known at compile time.
config SYS_CACHE_SIZE_AUTO
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
SYS_CACHELINE_SIZE = 0
SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
help
Select this (or let it be auto-selected by not defining any cache
sizes) in order to allow U-Boot to automatically detect the sizes
......
......@@ -12,4 +12,11 @@
#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
/*
* CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
* DMA buffer alignment. Satisfy those drivers by providing it as a synonym
* of ARCH_DMA_MINALIGN for now.
*/
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
#endif /* __MIPS_CACHE_H__ */
......@@ -9,23 +9,13 @@
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
static inline unsigned long icache_line_size(void)
{
return CONFIG_SYS_CACHELINE_SIZE;
}
static inline unsigned long dcache_line_size(void)
{
return CONFIG_SYS_CACHELINE_SIZE;
}
unsigned long conf1, il;
#else /* !CONFIG_SYS_CACHELINE_SIZE */
if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
return CONFIG_SYS_ICACHE_LINE_SIZE;
static inline unsigned long icache_line_size(void)
{
unsigned long conf1, il;
conf1 = read_c0_config1();
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il)
......@@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
static inline unsigned long dcache_line_size(void)
{
unsigned long conf1, dl;
if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
return CONFIG_SYS_DCACHE_LINE_SIZE;
conf1 = read_c0_config1();
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl)
......@@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void)
return 2 << dl;
}
#endif /* !CONFIG_SYS_CACHELINE_SIZE */
void flush_cache(ulong start_addr, ulong size)
{
unsigned long ilsize = icache_line_size();
......
......@@ -101,14 +101,14 @@
LEAF(mips_cache_reset)
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t2, CONFIG_SYS_ICACHE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE
li t8, CONFIG_SYS_ICACHE_LINE_SIZE
#else
l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t3, CONFIG_SYS_DCACHE_SIZE
li t9, CONFIG_SYS_CACHELINE_SIZE
li t9, CONFIG_SYS_DCACHE_LINE_SIZE
#else
l1_info t3, t9, MIPS_CONF1_DA_SHF
#endif
......
......@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
config SYS_DCACHE_SIZE
default 16384
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 16384
config SYS_CACHELINE_SIZE
config SYS_ICACHE_LINE_SIZE
default 32
menu "dbau1x00 board options"
......
......@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
config SYS_DCACHE_SIZE
default 16384
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 16384
config SYS_CACHELINE_SIZE
config SYS_ICACHE_LINE_SIZE
default 32
menu "vct board options"
......
......@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
config SYS_DCACHE_SIZE
default 16384
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 16384
config SYS_CACHELINE_SIZE
config SYS_ICACHE_LINE_SIZE
default 32
endif
......@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
config SYS_DCACHE_SIZE
default 32768
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 65536
config SYS_CACHELINE_SIZE
config SYS_ICACHE_LINE_SIZE
default 32
endif
......@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
config SYS_DCACHE_SIZE
default 32768
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 65536
config SYS_CACHELINE_SIZE
config SYS_ICACHE_LINE_SIZE
default 32
endif
......@@ -14,10 +14,13 @@ config SYS_TEXT_BASE
config SYS_DCACHE_SIZE
default 16384
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 16384
config SYS_CACHELINE_SIZE
config SYS_ICACHE_LINE_SIZE
default 32
endif
......@@ -18,10 +18,13 @@ config SYS_TEXT_BASE
config SYS_DCACHE_SIZE
default 32768
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 65536
config SYS_CACHELINE_SIZE
config SYS_ICACHE_LINE_SIZE
default 32
endif
......@@ -100,7 +100,6 @@
* USB Configuration
*/
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_SYS_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* File System Configuration
......
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