Commit 53c95384 authored by York Sun's avatar York Sun Committed by Tom Rini

powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig

Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.
Signed-off-by: 's avatarYork Sun <york.sun@nxp.com>
[trini: Migrate 8572]
Signed-off-by: 's avatarTom Rini <trini@konsulko.com>
parent 26e79b65
......@@ -376,15 +376,6 @@ The following options need to be configured:
Defines the string to utilize when trying to match PCIe device
tree nodes for the given platform.
CONFIG_SYS_PPC_E500_DEBUG_TLB
Enables a temporary TLB entry to be used during boot to work
around limitations in e500v1 and e500v2 external debugger
support. This reduces the portions of the boot code where
breakpoints and single stepping do not work. The value of this
symbol should be set to the TLB1 entry to be used for this
purpose.
CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set,
......
......@@ -338,14 +338,17 @@ config ARCH_BSC9131
config ARCH_BSC9132
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_C29X
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8536
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8540
bool
......@@ -358,10 +361,12 @@ config ARCH_MPC8541
config ARCH_MPC8544
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8548
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8555
bool
......@@ -382,26 +387,32 @@ config ARCH_MPC8569
config ARCH_MPC8572
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1010
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1011
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1020
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1021
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1022
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1023
bool
......@@ -410,14 +421,17 @@ config ARCH_P1023
config ARCH_P1024
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1025
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2020
bool
select FSL_LAW
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2041
bool
......@@ -655,6 +669,33 @@ config SYS_NUM_TLBCAMS
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
16 for other E500 SoCs.
config SYS_PPC_E500_USE_DEBUG_TLB
bool
config SYS_PPC_E500_DEBUG_TLB
int "Temporary TLB entry for external debugger"
depends on SYS_PPC_E500_USE_DEBUG_TLB
default 0 if ARCH_MPC8544 || ARCH_MPC8548
default 1 if ARCH_MPC8536
default 2 if ARCH_MPC8572 || \
ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020
default 3 if ARCH_P1010 || \
ARCH_BSC9132 || \
ARCH_C29X
help
Select a temporary TLB entry to be used during boot to work
around limitations in e500v1 and e500v2 external debugger
support. This reduces the portions of the boot code where
breakpoints and single stepping do not work. The value of this
symbol should be set to the TLB1 entry to be used for this
purpose. If unsure, do not change.
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
......
......@@ -25,7 +25,6 @@
#define CONFIG_SYS_FSL_SEC_MON_BE
#if defined(CONFIG_ARCH_MPC8536)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
......@@ -39,13 +38,11 @@
#elif defined(CONFIG_ARCH_MPC8544)
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8548)
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
......@@ -92,7 +89,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8572)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
......@@ -101,7 +97,6 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
......@@ -126,7 +121,6 @@
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
......@@ -137,7 +131,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1020)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
......@@ -150,7 +143,6 @@
#endif
#elif defined(CONFIG_ARCH_P1021)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
......@@ -164,7 +156,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
......@@ -192,7 +183,6 @@
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
......@@ -205,7 +195,6 @@
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
......@@ -218,7 +207,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
......@@ -433,7 +421,6 @@
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
......@@ -721,7 +708,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_SEC_COMPAT 6
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
......
......@@ -7209,7 +7209,6 @@ CONFIG_SYS_POWER_MANAGER
CONFIG_SYS_PPC4XX_USB_ADDR
CONFIG_SYS_PPC64
CONFIG_SYS_PPC_DDR_WIMGE
CONFIG_SYS_PPC_E500_DEBUG_TLB
CONFIG_SYS_PQSPAR
CONFIG_SYS_PRELIM_OR_AM
CONFIG_SYS_PROMPT_HUSH_PS2
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment