Commit 8993e54b authored by Rafal Jaworowski's avatar Rafal Jaworowski

[ADS5121] Support for the ADS5121 board

The following MPC5121e subsystems are supported:

- low-level CPU init
- NOR Boot Flash (common CFI driver)
- DDR SDRAM
- FEC
- I2C
- Watchdog
Signed-off-by: 's avatarGrzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: 's avatarRafal Jaworowski <raj@semihalf.com>
Signed-off-by: 's avatarJan Wrobel <wrr@semihalf.com>
parent 1863cfb7
......@@ -43,6 +43,14 @@ LIST_5xxx=" \
TQM5200S v38b \
"
#########################################################################
## MPC512x Systems
#########################################################################
LIST_512x=" \
ads5121 \
"
#########################################################################
## MPC8xx Systems
#########################################################################
......@@ -365,7 +373,7 @@ do
microblaze| \
mips|mips_el| \
nios|nios2| \
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
do
......
......@@ -641,6 +641,13 @@ motionpro_config: unconfig
@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
#########################################################################
## MPC512x Systems
#########################################################################
ads5121_config: unconfig
@$(MKCONFIG) ads5121 ppc mpc512x ads5121
#########################################################################
## MPC8xx Systems
#########################################################################
......
#
# (C) Copyright 2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* (C) Copyright 2007 DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <mpc512x.h>
#include <asm/bitops.h>
#include <command.h>
/* Clocks in use */
#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
CLOCK_SCCR1_LPC_EN | \
CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
CLOCK_SCCR1_PSCFIFO_EN | \
CLOCK_SCCR1_DDR_EN | \
CLOCK_SCCR1_FEC_EN)
#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
CLOCK_SCCR2_SPDIF_EN | \
CLOCK_SCCR2_I2C_EN)
#define CSAW_START(start) ((start) & 0xFFFF0000)
#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
long int fixed_sdram(void);
int board_early_init_f (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 lpcaw;
/*
* Initialize Local Window for the CPLD registers access (CS2 selects
* the CPLD chip)
*/
im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
im->lpc.cs_cfg[2] = CFG_CS2_CFG;
/*
* According to MPC5121e RM, configuring local access windows should
* be followed by a dummy read of the config register that was
* modified last and an isync
*/
lpcaw = im->sysconf.lpcs2aw;
__asm__ __volatile__ ("isync");
/*
* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
*
* Without this the flash identification routine fails, as it needs to issue
* write commands in order to establish the device ID.
*/
*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
/*
* Enable clocks
*/
im->clk.sccr[0] = SCCR1_CLOCKS_EN;
im->clk.sccr[1] = SCCR2_CLOCKS_EN;
return 0;
}
long int initdram (int board_type)
{
u32 msize = 0;
puts ("Initializing\n");
msize = fixed_sdram ();
puts (" DDR RAM: ");
return msize;
}
/*
* fixed sdram init -- the board doesn't use memory modules that have serial presence
* detect or similar mechanism for discovery of the DRAM settings
*/
long int fixed_sdram (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2 (msize);
u32 i;
/* Initialize IO Control */
im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
/* Initialize DDR Local Window */
im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
im->sysconf.ddrlaw.ar = msize_log2 - 1;
/*
* According to MPC5121e RM, configuring local access windows should
* be followed by a dummy read of the config register that was
* modified last and an isync
*/
i = im->sysconf.ddrlaw.ar;
__asm__ __volatile__ ("isync");
/* Enable DDR */
im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
/* Initialize DDR Priority Manager */
im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AU;
im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
/* Initialize MDDRC */
im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
/* Initialize DDR */
for (i = 0; i < 10; i++)
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_EM2;
im->mddrc.ddr_command = CFG_MICRON_EM3;
im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
im->mddrc.ddr_command = CFG_MICRON_RST_DLL;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_RFSH;
im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT;
for (i = 0; i < 10; i++)
im->mddrc.ddr_command = CFG_MICRON_NOP;
/* Start MDDRC */
im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
return msize;
}
int checkboard (void)
{
ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
brd_rev, cpld_rev);
return 0;
}
#
# (C) Copyright 2007 DENX Software Engineering
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFF00000
/*
* (C) Copyright 2007 DENX Software Engineering.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc512x/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)
#
# (C) Copyright 2007 DENX Software Engineering
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
#
# (C) Copyright 2007 DENX Software Engineering
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
-ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* (C) Copyright 2007 DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* CPU specific code for the MPC512x family.
*
* Derived from the MPC83xx code.
*/
#include <common.h>
#include <command.h>
#include <mpc512x.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
int checkcpu (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
ulong clock = gd->cpu_clk;
u32 pvr = get_pvr ();
u32 spridr = immr->sysconf.spridr;
char buf[32];
puts("CPU: ");
switch (spridr & 0xffff0000) {
case SPR_5121E:
puts ("MPC5121e ");
break;
default:
printf ("Unknown part ID %08x ", spridr & 0xffff0000);
}
printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
switch (pvr & 0xffff0000) {
case PVR_E300C4:
puts ("e300c4 ");
break;
default:
puts ("unknown ");
}
printf ("at %s MHz, CSB at %3d MHz\n", strmhz(buf, clock),
gd->csb_clk / 1000000);
return 0;
}
int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong msr;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
/* Interrupts and MMU off */
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
msr &= ~( MSR_EE | MSR_IR | MSR_DR);
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
/*
* Enable Reset Control Reg - "RSTE" is the magic word that let us go
*/
immap->reset.rpr = 0x52535445;
/* Verify Reset Control Reg is enabled */
while (!((immap->reset.rcer) & RCER_CRE))
;
printf ("Resetting the board.\n");
udelay(200);
/* Perform reset */
immap->reset.rcr = RCR_SWHR;
/* Unreached... */
return 1;
}
/*
* Get timebase clock frequency (like cpu_clk in Hz)
*/
unsigned long get_tbclk (void)
{
ulong tbclk;
tbclk = (gd->bus_clk + 3L) / 4L;
return tbclk;
}
#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
int re_enable = disable_interrupts ();
/* Reset watchdog */
volatile immap_t *immr = (immap_t *) CFG_IMMR;
immr->wdt.swsrr = 0x556c;
immr->wdt.swsrr = 0xaa39;
if (re_enable)
enable_interrupts ();
}
#endif
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* (C) Copyright 2007 DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Derived from the MPC83xx code.
*
*/
#include <common.h>
#include <mpc512x.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Set up the memory map, initialize registers,
*/
void cpu_init_f (volatile immap_t * im)
{
u32 ips_div;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
/* system performance tweaking */
#ifdef CFG_ACR_PIPE_DEP
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
(CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif
#ifdef CFG_ACR_RPTCNT
/* Arbiter repeat count */
im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) |
(CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
#endif
/* RSR - Reset Status Register - clear all status */
gd->reset_status = im->reset.rsr;
im->reset.rsr = ~(RSR_RES);
/*
* RMR - Reset Mode Register - enable checkstop reset
*/
im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT));
/* Set IPS-CSB divider: IPS = 1/2 CSB */
ips_div = im->clk.scfr[0];
ips_div &= ~(SCFR1_IPS_DIV_MASK);
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
im->clk.scfr[0] = ips_div;
/*
* Enable Time Base/Decrementer
*
* NOTICE: TB needs to be enabled as early as possible in order to
* have udelay() working; if not enabled, usually leads to a hang, like
* during FLASH chip identification etc.
*/
im->sysconf.spcr |= SPCR_TBEN;
}
int cpu_init_r (void)
{
return 0;
}
This diff is collapsed.
/*
* (C) Copyright 2003 - 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Derived from the MPC8xx driver's header file.
*/
#ifndef __MPC512X_FEC_H
#define __MPC512X_FEC_H
#include <common.h>
#include <mpc512x.h>
typedef unsigned long uint32;
typedef unsigned short uint16;
typedef unsigned char uint8;
typedef struct ethernet_register_set {
/* [10:2]addr = 00 */
/* Control and status Registers (offset 000-1FF) */
volatile uint32 fec_id; /* MBAR_ETH + 0x000 */
volatile uint32 ievent; /* MBAR_ETH + 0x004 */
volatile uint32 imask; /* MBAR_ETH + 0x008 */
volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */
volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */
volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */
volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */
volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */
volatile uint32 RES2[6]; /* MBAR_ETH + 0x028-03C */
volatile uint32 mii_data; /* MBAR_ETH + 0x040 */
volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */
volatile uint32 RES3[7]; /* MBAR_ETH + 0x048-060 */
volatile uint32 mib_control; /* MBAR_ETH + 0x064 */