Commit 8dda2e2f authored by Tom Rini's avatar Tom Rini

ARM: Migrate errata to Kconfig

This moves all of the current ARM errata from various header files and in to
Kconfig.  This allows for a minor amount of cleanup as we had some instances
where both a general common header file was enabling errata as well as the
board config.  We now just select these once at the higher level in Kconfig
Signed-off-by: default avatarTom Rini <trini@konsulko.com>
parent 0f12f101
......@@ -600,21 +600,6 @@ The following options need to be configured:
Thumb2 this flag will result in Thumb2 code generated by
GCC.
CONFIG_ARM_ERRATA_716044
CONFIG_ARM_ERRATA_742230
CONFIG_ARM_ERRATA_743622
CONFIG_ARM_ERRATA_751472
CONFIG_ARM_ERRATA_761320
CONFIG_ARM_ERRATA_773022
CONFIG_ARM_ERRATA_774769
CONFIG_ARM_ERRATA_794072
If set, the workarounds for these ARM errata are applied early
during U-Boot startup. Note that these options force the
workarounds to be applied; no CPU-type/version detection
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
COUNTER_FREQUENCY
Generic timer clock source frequency.
......@@ -623,15 +608,6 @@ The following options need to be configured:
different from COUNTER_FREQUENCY, and can only be determined
at run time.
NOTE: The following can be machine specific errata. These
do have ability to provide rudimentary version and machine
specific checks, but expect no product checks.
CONFIG_ARM_ERRATA_430973
CONFIG_ARM_ERRATA_454179
CONFIG_ARM_ERRATA_621766
CONFIG_ARM_ERRATA_798870
CONFIG_ARM_ERRATA_801819
- Tegra SoC options:
CONFIG_TEGRA_SUPPORT_NON_SECURE
......
......@@ -19,6 +19,72 @@ config HAS_VBAR
config HAS_THUMB2
bool
# If set, the workarounds for these ARM errata are applied early during U-Boot
# startup. Note that in general these options force the workarounds to be
# applied; no CPU-type/version detection exists, unlike the similar options in
# the Linux kernel. Do not set these options unless they apply! Also note that
# the following can be machine specific errata. These do have ability to
# provide rudimentary version and machine specific checks, but expect no
# product checks:
# CONFIG_ARM_ERRATA_430973
# CONFIG_ARM_ERRATA_454179
# CONFIG_ARM_ERRATA_621766
# CONFIG_ARM_ERRATA_798870
# CONFIG_ARM_ERRATA_801819
config ARM_ERRATA_430973
bool
config ARM_ERRATA_454179
bool
config ARM_ERRATA_621766
bool
config ARM_ERRATA_716044
bool
config ARM_ERRATA_742230
bool
config ARM_ERRATA_743622
bool
config ARM_ERRATA_751472
bool
config ARM_ERRATA_761320
bool
config ARM_ERRATA_773022
bool
config ARM_ERRATA_774769
bool
config ARM_ERRATA_794072
bool
config ARM_ERRATA_798870
bool
config ARM_ERRATA_801819
bool
config ARM_ERRATA_826974
bool
config ARM_ERRATA_828024
bool
config ARM_ERRATA_829520
bool
config ARM_ERRATA_833069
bool
config ARM_ERRATA_833471
bool
config CPU_ARM720T
bool
select SYS_CACHE_SHIFT_5
......@@ -569,6 +635,9 @@ config TARGET_MX53SMD
config OMAP34XX
bool "OMAP34XX SoC"
select ARCH_OMAP2
select ARM_ERRATA_430973
select ARM_ERRATA_454179
select ARM_ERRATA_621766
select USE_TINY_PRINTF
imply SPL_EXT_SUPPORT
imply SPL_FAT_SUPPORT
......@@ -602,6 +671,7 @@ config OMAP44XX
config OMAP54XX
bool "OMAP54XX SoC"
select ARCH_OMAP2
select ARM_ERRATA_798870
imply SPL_DISPLAY_PRINT
imply SPL_ENV_SUPPORT
imply SPL_EXT_SUPPORT
......
......@@ -3,6 +3,10 @@ if ARCH_MX6
config MX6
bool
default y
select ARM_ERRATA_743622 if !MX6UL
select ARM_ERRATA_751472 if !MX6UL
select ARM_ERRATA_761320 if !MX6UL
select ARM_ERRATA_794072 if !MX6UL
config MX6D
bool
......
......@@ -49,6 +49,10 @@ config ARCH_LS1046A
config ARCH_LS2080A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_826974
select ARM_ERRATA_828024
select ARM_ERRATA_829520
select ARM_ERRATA_833471
select FSL_LSCH3
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
......
......@@ -114,12 +114,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A008751
/* ARM A57 CORE ERRATA */
#define CONFIG_ARM_ERRATA_826974
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_829520
#define CONFIG_ARM_ERRATA_833471
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
......
......@@ -82,6 +82,8 @@ config TARGET_ODROID_XU3
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
select ARM_ERRATA_773022
select ARM_ERRATA_774769
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
......
......@@ -65,10 +65,15 @@ choice
config TEGRA20
bool "Tegra20 family"
select ARM_ERRATA_716044
select ARM_ERRATA_742230
select ARM_ERRATA_751472
select TEGRA_ARMV7_COMMON
config TEGRA30
bool "Tegra30 family"
select ARM_ERRATA_743622
select ARM_ERRATA_751472
select TEGRA_ARMV7_COMMON
config TEGRA114
......
......@@ -18,10 +18,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
......
......@@ -19,11 +19,6 @@
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
/*
......
......@@ -47,10 +47,6 @@
/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
/* CPU Errata */
#define CONFIG_ARM_ERRATA_773022
#define CONFIG_ARM_ERRATA_774769
/* Power */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
......
......@@ -25,10 +25,6 @@
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
......
......@@ -15,10 +15,6 @@
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_CM_T3517 /* working with CM-T3517 */
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
......
......@@ -15,10 +15,6 @@
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP3_MCX /* working with mcx */
#define CONFIG_OMAP_GPIO
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
......
......@@ -8,11 +8,6 @@
#define __MX6_COMMON_H
#ifndef CONFIG_MX6UL
#define CONFIG_ARM_ERRATA_743622
#define CONFIG_ARM_ERRATA_751472
#define CONFIG_ARM_ERRATA_794072
#define CONFIG_ARM_ERRATA_761320
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
......
......@@ -27,10 +27,6 @@
#define CONFIG_OMAP3430 /* which is in a 3430 */
#define CONFIG_OMAP3_RX51 /* working with RX51 */
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
......
......@@ -85,10 +85,6 @@
*/
#define CONFIG_OMAP /* This is TI OMAP core */
#define CONFIG_OMAP_GPIO
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
......
......@@ -17,9 +17,6 @@
*/
#define CONFIG_ARM_ARCH_CP15_ERRATA
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
/*
* Platform
......
......@@ -15,10 +15,6 @@
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
......
......@@ -19,10 +19,6 @@
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* Has an SDRC controller */
......
......@@ -9,13 +9,6 @@
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"
/*
* Errata configuration
*/
#define CONFIG_ARM_ERRATA_716044
#define CONFIG_ARM_ERRATA_742230
#define CONFIG_ARM_ERRATA_751472
/*
* NS16550 Configuration
*/
......
......@@ -9,12 +9,6 @@
#define _TEGRA30_COMMON_H_
#include "tegra-common.h"
/*
* Errata configuration
*/
#define CONFIG_ARM_ERRATA_743622
#define CONFIG_ARM_ERRATA_751472
/*
* NS16550 Configuration
*/
......
......@@ -21,11 +21,6 @@
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
/* The chip has SDRC controller */
#define CONFIG_SDRC
......
......@@ -17,9 +17,6 @@
#ifndef __CONFIG_TI_OMAP5_COMMON_H
#define __CONFIG_TI_OMAP5_COMMON_H
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_798870
/* Use General purpose timer 1 */
#define CONFIG_SYS_TIMERBASE GPT2_BASE
......
......@@ -19,10 +19,6 @@
/* High Level Configuration Options */
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_OMAP /* in a TI OMAP core */
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
/*
......
......@@ -141,24 +141,6 @@ CONFIG_ARMV8_SWITCH_TO_EL1
CONFIG_ARM_ARCH_CP15_ERRATA
CONFIG_ARM_ASM_UNIFIED
CONFIG_ARM_DCC
CONFIG_ARM_ERRATA_430973
CONFIG_ARM_ERRATA_454179
CONFIG_ARM_ERRATA_621766
CONFIG_ARM_ERRATA_716044
CONFIG_ARM_ERRATA_742230
CONFIG_ARM_ERRATA_743622
CONFIG_ARM_ERRATA_751472
CONFIG_ARM_ERRATA_761320
CONFIG_ARM_ERRATA_773022
CONFIG_ARM_ERRATA_774769
CONFIG_ARM_ERRATA_794072
CONFIG_ARM_ERRATA_798870
CONFIG_ARM_ERRATA_801819
CONFIG_ARM_ERRATA_826974
CONFIG_ARM_ERRATA_828024
CONFIG_ARM_ERRATA_829520
CONFIG_ARM_ERRATA_833069
CONFIG_ARM_ERRATA_833471
CONFIG_ARM_FREQ
CONFIG_ARM_GIC_BASE_ADDRESS
CONFIG_ARM_PL180_MMCI
......
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