Commit 9ee16897 authored by Lucile Quirion's avatar Lucile Quirion Committed by Stefano Babic

ARM: ts4800: add basic board support

This commit adds basic support including:
MMC, Serial console, TS4800 watchdog

The config use CONFIG_SKIP_LOWLEVEL_INIT as U-boot is used as a second
stage bootloader.
Signed-off-by: default avatarLucile Quirion <lucile.quirion@savoirfairelinux.com>
signed-off-by: default avatarDamien Riegel <damien.riegel@savoirfairelinux.com>
Cc: Stefano Babic <sbabic@denx.de>
parent 0d8c32dd
......@@ -667,6 +667,10 @@ config TARGET_SNOWBALL
bool "Support snowball"
select CPU_V7
config TARGET_TS4800
bool "Support TS4800"
select CPU_V7
config TARGET_U8500_HREF
bool "Support u8500_href"
select CPU_V7
......@@ -991,6 +995,7 @@ source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
source "board/trizepsiv/Kconfig"
source "board/technologic/ts4800/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
source "board/udoo/Kconfig"
source "board/vpac270/Kconfig"
......
if TARGET_TS4800
config SYS_BOARD
default "ts4800"
config SYS_VENDOR
default "technologic"
config SYS_SOC
default "mx5"
config SYS_CONFIG_NAME
default "ts4800"
endif
TS4800 BOARD
M: Lucile Quirion <lucile.quirion@savoirfairelinux.com>
S: Maintained
F: board/ts/ts4800/
F: include/configs/ts4800.h
F: configs/ts4800_defconfig
#
# (C) Copyright 2015 Savoir-faire Linux
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ts4800.o
/*
* (C) Copyright 2015 Savoir-faire Linux Inc.
*
* Derived from MX51EVK code by
* Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx51.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/imx-common/mx5_video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <mc13892.h>
#include "ts4800.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
};
#endif
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
u32 get_board_rev(void)
{
u32 rev = get_cpu_rev();
if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
return rev;
}
#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
static void setup_iomux_uart(void)
{
static const iomux_v3_cfg_t uart_pads[] = {
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
#ifdef CONFIG_FSL_ESDHC
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
NO_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(1, 0));
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
NO_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(1, 6));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
else
ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
return ret;
}
int board_mmc_init(bd_t *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
};
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int checkboard(void)
{
puts("Board: TS4800\n");
return 0;
}
void hw_watchdog_reset(void)
{
struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
/* feed the watchdog for another 10s */
writew(0x2, &wtd->feed);
}
void hw_watchdog_init(void)
{
return;
}
/*
* (C) Copyright 2015 Savoir-faire Linux Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TS4800_H
#define _TS4800_H
#define TS4800_SYSCON_BASE 0xb0010000
struct ts4800_wtd_regs {
u16 feed;
};
#endif
CONFIG_ARM=y
CONFIG_TARGET_TS4800=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
/*
* Copyright (C) 2015, Savoir-faire Linux Inc.
*
* Derived from MX51EVK code by
* Guennadi Liakhovetski <lg@denx.de>
* Freescale Semiconductor, Inc.
*
* Configuration settings for the TS4800 Board
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_MX51
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_NO_FLASH /* No NOR Flash */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-boot is a 2nd stage bootloader */
#define CONFIG_HW_WATCHDOG
#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX
/* text base address used when linking */
#define CONFIG_SYS_TEXT_BASE 0x90008000
#include <asm/arch/imx-regs.h>
/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
/* use common/board_f.c instead of arch/<arch>/lib/<board>.c */
#define CONFIG_SYS_GENERIC_BOARD
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/*
* Hardware drivers
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_MXC_GPIO
/*
* SPI Configs
* */
#define CONFIG_HARD_SPI /* puts SPI: ready */
#define CONFIG_MXC_SPI /* driver for the SPI controllers*/
#define CONFIG_CMD_SPI /* SPI serial bus support */
/*
* MMC Configs
* */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */
#define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */
#define CONFIG_BAUDRATE 115200
/***********************************************************
* Command definition
***********************************************************/
#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
/* Environment variables */
#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=uImage\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
"mmcargs=setenv bootargs root=/dev/mmcblk0p2 rootwait rw\0" \
"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs addtty; " \
"bootm; "
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"fi; " \
"fi; " \
"fi; "
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_CMDLINE_EDITING
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Low level init */
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
#define CONFIG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
* Environment organization
*/
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
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