Commit d87080b7 authored by Wolfgang Denk's avatar Wolfgang Denk

GCC-4.x fixes: clean up global data pointer initialization for all boards.

parent f6dbbe98
......@@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4:
======================================================================
* GCC-4.x fixes: clean up global data pointer initialization for all
boards
* Update for Delta board:
- redundant NAND environment
- misc Monahans cleanups (remove dead code etc.)
......
......@@ -3309,6 +3309,8 @@ On ARM, the following registers are used:
==> U-Boot will use R8 to hold a pointer to the global data
NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
or current versions of GCC may "optimize" the code too much.
Memory Management:
------------------
......
/*
* (C) Copyright 2002
* Hyperion Entertainment, ThomasF@hyperion-entertainment.com
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
......@@ -88,8 +89,6 @@ long initdram (int board_type)
void after_reloc (ulong dest_addr, gd_t *gd)
{
/* HJF: DECLARE_GLOBAL_DATA_PTR; */
board_init_r (gd, dest_addr);
}
......
......@@ -29,6 +29,8 @@
#include "smbus.h"
#include "via686.h"
DECLARE_GLOBAL_DATA_PTR;
#undef DEBUG
struct dimm_bank {
......@@ -82,7 +84,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte)
long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
{
DECLARE_GLOBAL_DATA_PTR;
int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
uint32 busclock = gd->bus_clk;
uint32 memclock = busclock;
......@@ -394,8 +395,6 @@ uint32 burst_to_len (uint32 support)
long articiaS_ram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
register uint32 i;
register uint32 value1;
register uint32 value2;
......
......@@ -26,6 +26,8 @@
#include "memio.h"
#include "articiaS.h"
DECLARE_GLOBAL_DATA_PTR;
#undef ARTICIA_PCI_DEBUG
#ifdef ARTICIA_PCI_DEBUG
......@@ -493,8 +495,6 @@ pci_dev_t video_dev;
int articiaS_init_vga (void)
{
DECLARE_GLOBAL_DATA_PTR;
extern void shutdown_bios(void);
pci_dev_t dev = ~0;
int busnr = 0;
......
......@@ -3,6 +3,7 @@
#include "../disk/part_amiga.h"
#include <asm/cache.h>
DECLARE_GLOBAL_DATA_PTR;
#undef BOOTA_DEBUG
......@@ -108,8 +109,6 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
s = getenv ("autostart");
if (s && strcmp (s, "yes") == 0) {
DECLARE_GLOBAL_DATA_PTR;
void (*boot) (bd_t *, char *, block_dev_desc_t *);
char *args;
......
......@@ -4,6 +4,8 @@
#include "memio.h"
#include "articiaS.h"
DECLARE_GLOBAL_DATA_PTR;
#ifndef CFG_NS16550
static uint32 ComPort1;
......@@ -150,8 +152,6 @@ const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2;
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
uint32 clock_divisor = 115200 / gd->baudrate;
NS16550_init (Com0, clock_divisor);
......@@ -239,8 +239,6 @@ void serial_puts (const char *string)
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
uint32 clock_divisor = 115200 / gd->baudrate;
NS16550_init (Com0, clock_divisor);
......
......@@ -28,6 +28,8 @@
#include "via686.h"
#include "i8259.h"
DECLARE_GLOBAL_DATA_PTR;
#undef VIA_DEBUG
#ifdef VIA_DEBUG
......@@ -226,33 +228,31 @@ __asm (" .globl via_calibrate_time_base \n"
extern unsigned long via_calibrate_time_base(void);
void via_calibrate_bus_freq(void)
void via_calibrate_bus_freq (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned long tb;
unsigned long tb;
/* This is 20 microseconds */
#define CALIBRATE_TIME 28636
/* This is 20 microseconds */
#define CALIBRATE_TIME 28636
/* Enable the timer (and disable speaker) */
unsigned char c;
/* Enable the timer (and disable speaker) */
unsigned char c;
c = in_byte(0x61);
out_byte(0x61, ((c & ~0x02) | 0x01));
c = in_byte (0x61);
out_byte (0x61, ((c & ~0x02) | 0x01));
/* Set timer 2 to low/high writing */
out_byte(0x43, 0xb0);
out_byte(0x42, CALIBRATE_TIME & 0xff);
out_byte(0x42, CALIBRATE_TIME >>8);
/* Set timer 2 to low/high writing */
out_byte (0x43, 0xb0);
out_byte (0x42, CALIBRATE_TIME & 0xff);
out_byte (0x42, CALIBRATE_TIME >> 8);
/* Read the time base */
tb = via_calibrate_time_base();
/* Read the time base */
tb = via_calibrate_time_base ();
if (tb >= 700000)
gd->bus_clk = 133333333;
else
gd->bus_clk = 100000000;
if (tb >= 700000)
gd->bus_clk = 133333333;
else
gd->bus_clk = 100000000;
}
......
......@@ -26,6 +26,8 @@
#include "memio.h"
#include <part.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned char *cursor_position;
unsigned int cursor_row;
unsigned int cursor_col;
......@@ -480,7 +482,6 @@ extern char version_string[];
void video_banner(void)
{
block_dev_desc_t *ide;
DECLARE_GLOBAL_DATA_PTR;
int i;
char *s;
int maxdev;
......
......@@ -45,13 +45,13 @@
#include "ns16550.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_MPSC
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
int clock_divisor = 230400 / gd->baudrate;
#endif
......@@ -88,8 +88,6 @@ int serial_tstc (void)
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
......@@ -97,8 +95,6 @@ void serial_setbrg (void)
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = 230400 / gd->baudrate;
#ifdef CFG_INIT_CHAN1
......@@ -130,8 +126,6 @@ int serial_tstc (void)
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = 230400 / gd->baudrate;
#ifdef CFG_INIT_CHAN1
......
......@@ -42,6 +42,8 @@
#include "../include/memory.h"
DECLARE_GLOBAL_DATA_PTR;
/* Define this if you wish to use the MPSC as a register based UART.
* This will force the serial port to not use the SDMA engine at all.
*/
......@@ -114,9 +116,7 @@ static void mpsc_debug_init (void)
/* Clear the CFR (CHR4) */
/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&". Assuming "= &"
REG_GAP));
temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
temp &= 0xffffff00;
temp |= BIT29;
GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
......@@ -158,7 +158,6 @@ char mpsc_getchar_debug (void)
* global variables [josh] */
int mpsc_putchar_early (char ch)
{
DECLARE_GLOBAL_DATA_PTR;
int mpsc = CHANNEL;
int temp =
GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
......@@ -511,7 +510,6 @@ void mpsc_init2 (void)
int galbrg_set_baudrate (int channel, int rate)
{
DECLARE_GLOBAL_DATA_PTR;
int clock;
galbrg_disable (channel); /*ok */
......
......@@ -732,6 +732,7 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
pkt_info.byte_cnt = dataSize;
pkt_info.buf_ptr = (unsigned int) dataPtr;
pkt_info.return_info = 0;
status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
......
......@@ -42,6 +42,8 @@
#include "64360.h"
#include "mv_regs.h"
DECLARE_GLOBAL_DATA_PTR;
#undef DEBUG
#define MAP_PCI
......@@ -246,8 +248,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte)
/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned long spd_checksum;
#ifdef ZUMA_NTL
......
......@@ -42,6 +42,8 @@
#include "../include/memory.h"
DECLARE_GLOBAL_DATA_PTR;
/* Define this if you wish to use the MPSC as a register based UART.
* This will force the serial port to not use the SDMA engine at all.
*/
......@@ -114,9 +116,7 @@ static void mpsc_debug_init (void)
/* Clear the CFR (CHR4) */
/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&". Assuming "= &"
REG_GAP));
temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
temp &= 0xffffff00;
temp |= BIT29;
GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
......@@ -158,7 +158,6 @@ char mpsc_getchar_debug (void)
* global variables [josh] */
int mpsc_putchar_early (char ch)
{
DECLARE_GLOBAL_DATA_PTR;
int mpsc = CHANNEL;
int temp =
GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
......@@ -511,7 +510,6 @@ void mpsc_init2 (void)
int galbrg_set_baudrate (int channel, int rate)
{
DECLARE_GLOBAL_DATA_PTR;
int clock;
galbrg_disable (channel); /*ok */
......
......@@ -731,6 +731,7 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
pkt_info.byte_cnt = dataSize;
pkt_info.buf_ptr = (unsigned int) dataPtr;
pkt_info.return_info = 0;
status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
......
......@@ -42,6 +42,8 @@
#include "64460.h"
#include "mv_regs.h"
DECLARE_GLOBAL_DATA_PTR;
#undef DEBUG
#define MAP_PCI
......@@ -246,8 +248,6 @@ static inline unsigned short NSto10PS (unsigned char spd_byte)
/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned long spd_checksum;
#ifdef ZUMA_NTL
......
......@@ -30,6 +30,8 @@
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
......@@ -38,8 +40,6 @@
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
......@@ -62,8 +62,6 @@ int board_late_init(void)
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
......
......@@ -28,6 +28,8 @@
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
DECLARE_GLOBAL_DATA_PTR;
long int fixed_sdram(void);
int board_early_init_f(void)
......@@ -107,7 +109,7 @@ long int initdram(int board_type)
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram(0);
dram_size = spd_sdram();
#else
dram_size = fixed_sdram();
#endif
......@@ -235,8 +237,6 @@ int pci_pre_init(struct pci_controller *hose)
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
DECLARE_GLOBAL_DATA_PTR;
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
......
......@@ -28,6 +28,7 @@
#include <spd_sdram.h>
#include "epld.h"
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
......@@ -291,8 +292,6 @@ int pci_pre_init( struct pci_controller *hose )
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
DECLARE_GLOBAL_DATA_PTR;
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
......
......@@ -30,6 +30,8 @@
#include <spd_sdram.h>
#include <ppc4xx_enet.h>
DECLARE_GLOBAL_DATA_PTR;
#define BOOT_SMALL_FLASH 32 /* 00100000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
......@@ -204,7 +206,7 @@ long int initdram (int board_type)
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram (0);
dram_size = spd_sdram ();
#else
dram_size = fixed_sdram ();
#endif
......@@ -334,8 +336,6 @@ int pci_pre_init(struct pci_controller * hose )
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
DECLARE_GLOBAL_DATA_PTR;
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
......
......@@ -99,7 +99,7 @@ void sdram_init(void)
*/
long int initdram(int board_type)
{
return spd_sdram(0);
return spd_sdram();
}
int testdram(void)
......
......@@ -24,6 +24,8 @@
#include <asm/processor.h>
#include <spd_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
int board_early_init_f(void)
......@@ -136,7 +138,6 @@ int board_early_init_f(void)
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
uint pbcr;
int size_val = 0;
......
......@@ -24,6 +24,8 @@
#include <asm/processor.h>
#include <spd_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
int board_early_init_f(void)
......@@ -132,7 +134,6 @@ int board_early_init_f(void)
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
uint pbcr;
int size_val = 0;
......
......@@ -27,9 +27,7 @@
#include <ns16550.h>
#if 0
#include "serial.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
const NS16550_t COM_PORTS[] =
{ (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
......@@ -40,8 +38,6 @@ static int gComPort = 0;
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
(void) NS16550_init (COM_PORTS[0], clock_divisor);
......@@ -71,8 +67,6 @@ int serial_tstc (void)
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
#ifdef CFG_INIT_CHAN1
......
......@@ -28,6 +28,8 @@
#include <common.h>
#include <clps7111.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
......@@ -37,8 +39,6 @@
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* Activate LED flasher */
IO_LEDFLSH = 0x40;
......@@ -53,8 +53,6 @@ int board_init (void)
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
......
......@@ -27,6 +27,8 @@
#include <common.h>
#include <SA-1100.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
......@@ -99,8 +101,6 @@ neponset_init(void)
int
board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
gd->bd->bi_boot_params = 0xc0000100;
......@@ -112,8 +112,6 @@ board_init(void)
int
dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
......
......@@ -27,6 +27,8 @@
#include <at91rm9200_net.h>
#include <dm9161.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
......@@ -34,8 +36,6 @@
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* Enable Ctrlc */
console_init_f ();
......@@ -56,8 +56,6 @@ int board_init (void)
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
return 0;
......
......@@ -24,6 +24,8 @@
#include <common.h>
#include "ns16550.h"
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_CONS_INDEX == 1
static struct NS16550 *console =
(struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
......@@ -38,8 +40,6 @@ extern ulong get_bus_freq (ulong);
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = gd->bus_clk / 16 / gd->baudrate;
NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor);
......@@ -75,8 +75,6 @@ int serial_tstc (void)
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;