Commit da6e2fab authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-mips

parents 653bb0d9 f1b65c98
......@@ -33,6 +33,9 @@ config TARGET_MALTA
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS32_R6
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
select SUPPORTS_CPU_MIPS64_R6
select SWAP_IO_SPACE
select MIPS_L1_CACHE_SHIFT_6
......@@ -225,6 +228,9 @@ config MIPS_TUNE_14KC
config MIPS_TUNE_24KC
bool
config MIPS_TUNE_34KC
bool
config MIPS_TUNE_74KC
bool
......@@ -240,6 +246,40 @@ config SWAP_IO_SPACE
config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
config SYS_DCACHE_SIZE
int
default 0
help
The total size of the L1 Dcache, if known at compile time.
config SYS_DCACHE_LINE_SIZE
hex
default 0
help
The size of L1 Dcache lines, if known at compile time.
config SYS_ICACHE_SIZE
int
default 0
help
The total size of the L1 ICache, if known at compile time.
config SYS_ICACHE_LINE_SIZE
int
default 0
help
The size of L1 Icache lines, if known at compile time.
config SYS_CACHE_SIZE_AUTO
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
help
Select this (or let it be auto-selected by not defining any cache
sizes) in order to allow U-Boot to automatically detect the sizes
of caches at runtime. This has a small cost in code size & runtime
so if you know the cache configuration for your system at compile
time it would be beneficial to configure it.
config MIPS_L1_CACHE_SHIFT_4
bool
......
......@@ -34,6 +34,7 @@ arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
# Include default header files
......
......@@ -65,7 +65,7 @@ else
PF_ABICALLS := -mabicalls
PF_PIC := -fpic
PF_PIE := -pie
PF_OBJCOPY := -j .got -j .u_boot_list -j .rel.dyn -j .padding
PF_OBJCOPY := -j .got -j .rel.dyn -j .padding
PF_OBJCOPY += -j .dtb.init.rodata
endif
......@@ -74,4 +74,5 @@ PLATFORM_CPPFLAGS += -msoft-float
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections $(PF_PIE)
OBJCOPYFLAGS += -j .text -j .rodata -j .data $(PF_OBJCOPY)
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list
OBJCOPYFLAGS += $(PF_OBJCOPY)
/*
* SPDX-License-Identifier: GPL-2.0+
*/
MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text : {
*(.text*)
} > .spl_mem
. = ALIGN(4);
.rodata : {
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} > .spl_mem
. = ALIGN(4);
.data : {
*(SORT_BY_ALIGNMENT(.data*))
*(SORT_BY_ALIGNMENT(.sdata*))
} > .spl_mem
#ifdef CONFIG_SPL_DM
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
} > .spl_mem
#endif
. = ALIGN(4);
__image_copy_end = .;
.bss (NOLOAD) : {
__bss_start = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end = .;
} > .bss_mem
.rel.dyn (NOLOAD) : {
*(.rel.dyn)
}
.dynsym : {
*(.dynsym)
}
.dynbss : {
*(.dynbss)
}
.dynstr : {
*(.dynstr)
}
.dynamic : {
*(.dynamic)
}
.plt : {
*(.plt)
}
.interp : {
*(.interp)
}
.gnu : {
*(.gnu*)
}
.MIPS.stubs : {
*(.MIPS.stubs)
}
.hash : {
*(.hash)
}
}
......@@ -41,3 +41,8 @@
reg = <0>;
};
};
&gmac0 {
phy-mode = "rmii";
status = "okay";
};
......@@ -75,7 +75,7 @@
};
gmac0: eth@0x19000000 {
compatible = "qca,ag7240-mac";
compatible = "qca,ag933x-mac";
reg = <0x19000000 0x200>;
phy = <&phy0>;
phy-mode = "rmii";
......@@ -92,7 +92,7 @@
};
gmac1: eth@0x1a000000 {
compatible = "qca,ag7240-mac";
compatible = "qca,ag933x-mac";
reg = <0x1a000000 0x200>;
phy = <&phy0>;
phy-mode = "rgmii";
......
......@@ -12,4 +12,11 @@
#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
/*
* CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
* DMA buffer alignment. Satisfy those drivers by providing it as a synonym
* of ARCH_DMA_MINALIGN for now.
*/
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
#endif /* __MIPS_CACHE_H__ */
......@@ -92,11 +92,8 @@ static inline unsigned long virt_to_phys(volatile const void *address)
#ifdef CONFIG_64BIT
if (addr < CKSEG0)
return XPHYSADDR(addr);
return CPHYSADDR(addr);
#else
return addr - PAGE_OFFSET + PHYS_OFFSET;
#endif
return CPHYSADDR(addr);
}
/*
......
/*
* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de
*/
static inline unsigned long bss_start(void)
{
extern char __bss_start[];
return (unsigned long) &__bss_start;
}
#ifndef _U_BOOT_MIPS_H_
#define _U_BOOT_MIPS_H_
static inline unsigned long bss_end(void)
{
extern ulong __bss_end;
return (unsigned long) &__bss_end;
}
static inline unsigned long image_copy_end(void)
{
extern char __image_copy_end[];
return (unsigned long) &__image_copy_end;
}
#endif /* _U_BOOT_MIPS_H_ */
......@@ -9,23 +9,13 @@
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
#ifdef CONFIG_SYS_CACHELINE_SIZE
static inline unsigned long icache_line_size(void)
{
return CONFIG_SYS_CACHELINE_SIZE;
}
static inline unsigned long dcache_line_size(void)
{
return CONFIG_SYS_CACHELINE_SIZE;
}
unsigned long conf1, il;
#else /* !CONFIG_SYS_CACHELINE_SIZE */
if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
return CONFIG_SYS_ICACHE_LINE_SIZE;
static inline unsigned long icache_line_size(void)
{
unsigned long conf1, il;
conf1 = read_c0_config1();
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il)
......@@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
static inline unsigned long dcache_line_size(void)
{
unsigned long conf1, dl;
if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
return CONFIG_SYS_DCACHE_LINE_SIZE;
conf1 = read_c0_config1();
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl)
......@@ -43,84 +37,59 @@ static inline unsigned long dcache_line_size(void)
return 2 << dl;
}
#endif /* !CONFIG_SYS_CACHELINE_SIZE */
#define cache_loop(start, end, lsize, ops...) do { \
const void *addr = (const void *)(start & ~(lsize - 1)); \
const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
const unsigned int cache_ops[] = { ops }; \
unsigned int i; \
\
for (; addr <= aend; addr += lsize) { \
for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
mips_cache(cache_ops[i], addr); \
} \
} while (0)
void flush_cache(ulong start_addr, ulong size)
{
unsigned long ilsize = icache_line_size();
unsigned long dlsize = dcache_line_size();
const void *addr, *aend;
/* aend will be miscalculated when size is zero, so we return here */
if (size == 0)
return;
addr = (const void *)(start_addr & ~(dlsize - 1));
aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
if (ilsize == dlsize) {
/* flush I-cache & D-cache simultaneously */
while (1) {
mips_cache(HIT_WRITEBACK_INV_D, addr);
mips_cache(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += dlsize;
}
cache_loop(start_addr, start_addr + size, ilsize,
HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
return;
}
/* flush D-cache */
while (1) {
mips_cache(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += dlsize;
}
cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
/* flush I-cache */
addr = (const void *)(start_addr & ~(ilsize - 1));
aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
while (1) {
mips_cache(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += ilsize;
}
cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
}
void flush_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
const void *addr = (const void *)(start_addr & ~(lsize - 1));
const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
/* aend will be miscalculated when size is zero, so we return here */
if (start_addr == stop)
return;
while (1) {
mips_cache(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += lsize;
}
cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
const void *addr = (const void *)(start_addr & ~(lsize - 1));
const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
/* aend will be miscalculated when size is zero, so we return here */
if (start_addr == stop)
return;
while (1) {
mips_cache(HIT_INVALIDATE_D, addr);
if (addr == aend)
break;
addr += lsize;
}
cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
}
......@@ -99,16 +99,16 @@
*
*/
LEAF(mips_cache_reset)
#ifdef CONFIG_SYS_ICACHE_SIZE
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t2, CONFIG_SYS_ICACHE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE
li t8, CONFIG_SYS_ICACHE_LINE_SIZE
#else
l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif
#ifdef CONFIG_SYS_DCACHE_SIZE
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t3, CONFIG_SYS_DCACHE_SIZE
li t9, CONFIG_SYS_CACHELINE_SIZE
li t9, CONFIG_SYS_DCACHE_LINE_SIZE
#else
l1_info t3, t9, MIPS_CONF1_DA_SHF
#endif
......@@ -116,7 +116,7 @@ LEAF(mips_cache_reset)
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Determine the largest L1 cache size */
#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
li v0, CONFIG_SYS_ICACHE_SIZE
#else
......
......@@ -9,7 +9,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/reset.h>
#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -17,7 +17,7 @@ static u32 ar933x_get_xtal(void)
{
u32 val;
val = get_bootstrap();
val = ath79_get_bootstrap();
if (val & AR933X_BOOTSTRAP_REF_CLK_40)
return 40000000;
else
......
......@@ -10,7 +10,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/reset.h>
#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -114,7 +114,7 @@ void ddr_init(void)
writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
val = get_bootstrap();
val = ath79_get_bootstrap();
if (val & AR933X_BOOTSTRAP_DDR2) {
/* AHB maximum timeout */
writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
......
......@@ -9,7 +9,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/reset.h>
#include <mach/ath79.h>
#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -119,7 +119,7 @@ void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
/* Test for 40MHz XTAL */
reg = get_bootstrap();
reg = ath79_get_bootstrap();
if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
xtal_40 = 1;
cpu_srif = 0x41c00000;
......@@ -214,7 +214,7 @@ static u32 ar934x_get_xtal(void)
{
u32 val;
val = get_bootstrap();
val = ath79_get_bootstrap();
if (val & AR934X_BOOTSTRAP_REF_CLK_40)
return 40000000;
else
......
......@@ -11,7 +11,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/reset.h>
#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -45,7 +45,7 @@ void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);
reg = get_bootstrap();
reg = ath79_get_bootstrap();
if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */
if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */
memtype = AR934X_DDR1;
......
......@@ -331,6 +331,7 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLK_CTRL_REG 0x08
#define AR933X_PLL_DITHER_FRAC_REG 0x10
#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
......
......@@ -140,6 +140,7 @@ static inline int soc_is_qca956x(void)
return soc_is_tp9343() || soc_is_qca9561();
}
u32 ath79_get_bootstrap(void);
int ath79_eth_reset(void);
int ath79_usb_reset(void);
......
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_MACH_RESET_H
#define __ASM_MACH_RESET_H
#include <linux/types.h>
u32 get_bootstrap(void);
#endif /* __ASM_MACH_RESET_H */
......@@ -9,7 +9,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/reset.h>
#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -17,7 +17,7 @@ static u32 qca953x_get_xtal(void)
{
u32 val;
val = get_bootstrap();
val = ath79_get_bootstrap();
if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
return 40000000;
else
......
......@@ -10,7 +10,7 @@
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/reset.h>
#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -226,7 +226,7 @@ void ddr_init(void)
regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);
val = get_bootstrap();
val = ath79_get_bootstrap();
if (val & QCA953X_BOOTSTRAP_DDR1) {
writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
udelay(10);
......
......@@ -45,7 +45,7 @@ void _machine_restart(void)
/* NOP */;
}
u32 get_bootstrap(void)
u32 ath79_get_bootstrap(void)
{
void __iomem *base;
u32 reg = 0;
......@@ -89,7 +89,7 @@ static int eth_init_ar933x(void)
mdelay(10);
/* Get Atheros S26 PHY out of reset. */
clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
0x1f, 0x10);
mdelay(10);
......@@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
return 0;
}
static int eth_init_qca953x(void)
{
void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
MAP_NOCACHE);
const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
QCA953X_RESET_ETH_SWITCH_ANALOG |
QCA953X_RESET_ETH_SWITCH;
setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
mdelay(1);
clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
mdelay(1);
return 0;
}
int ath79_eth_reset(void)
{
/*
......@@ -146,6 +163,8 @@ int ath79_eth_reset(void)
return eth_init_ar933x();
if (soc_is_ar934x())
return eth_init_ar934x();
if (soc_is_qca953x())
return eth_init_qca953x();
return -EINVAL;
}
......@@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
return 0;
}
static int usb_reset_qca953x(void __iomem *reset_regs)
{
void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
MAP_NOCACHE);
clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
0xf00, 0x200);
mdelay(10);
/* Ungate the USB block */
setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
QCA953X_RESET_USBSUS_OVERRIDE);
mdelay(1);
clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
QCA953X_RESET_USB_PHY);
mdelay(1);
clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
QCA953X_RESET_USB_PHY_ANALOG);
mdelay(1);
clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
QCA953X_RESET_USB_HOST);
mdelay(1);
clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
mdelay(1);
return 0;
}
int ath79_usb_reset(void)
{
void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
......@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
return usb_reset_ar933x(reset_regs);
if (soc_is_ar934x())
return usb_reset_ar934x(reset_regs);
if (soc_is_qca953x())
return usb_reset_qca953x(reset_regs);
return -EINVAL;
}
......@@ -12,6 +12,18 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0xbfc00000
config SYS_DCACHE_SIZE
default 16384
config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 16384
config SYS_ICACHE_LINE_SIZE
default 32
menu "dbau1x00 board options"
choice
......
......@@ -10,6 +10,7 @@ config SYS_CONFIG_NAME
default "malta"
config SYS_TEXT_BASE
default 0xbe000000
default 0xbe000000 if 32BIT
default 0xffffffffbe000000 if 64BIT
endif
......@@ -10,6 +10,7 @@
#include <pci.h>
#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/malta.h>
#include <asm/mipsregs.h>
......@@ -34,7 +35,7 @@ lowlevel_init:
mtc0 t0, CP0_CONFIG, 2
/* detect the core card */
li t0, KSEG1ADDR(MALTA_REVISION)
PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
lw t0, 0(t0)
srl t0, t0, MALTA_REVISION_CORID_SHF
andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
......@@ -68,12 +69,12 @@ lowlevel_init:
*/
_gt64120:
/* move GT64120 registers from 0x14000000 to 0x1be00000 */
li t1, KSEG1ADDR(GT_DEF_BASE)
PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
li t0, CPU_TO_GT32(0xdf000000)
sw t0, GT_ISD_OFS(t1)
/* setup MEM-to-PCI0 mapping */
li t1, KSEG1ADDR(MALTA_GT_BASE)
PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
/* setup PCI0 io window to 0x18000000-0x181fffff */
li t0, CPU_TO_GT32(0xc0000000)
......@@ -100,7 +101,7 @@ _gt64120:
*/
_msc01:
/* setup peripheral bus controller clock divide */
li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
sw t1, MSC01_PBC_CLKCFG_OFS(t0)
......@@ -122,7 +123,7 @@ _msc01:
sw t1, MSC01_PBC_CS0CFG_OFS(t0)
/* setup basic address decode */
li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
li t1, 0x0
li t2, -CONFIG_SYS_MEM_SIZE
sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
......@@ -157,7 +158,7 @@ _msc01:
sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
/* setup PCI memory */
li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
li t1, MALTA_MSC01_PCIMEM_BASE