Commit f3c264f9 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-x86

parents e4a94ce4 d3d66472
......@@ -155,7 +155,7 @@ u32 acpi_fill_madt(u32 current)
current += acpi_create_madt_lapics(current);
current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
2, IO_APIC_ADDR, 0);
io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
current += acpi_create_madt_irq_overrides(current);
......
......@@ -6,3 +6,4 @@
obj-y += car.o dram.o irq.o msg_port.o quark.o
obj-y += mrc.o mrc_util.o hte.o smc.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/acpi_table.h>
#include <asm/ioapic.h>
#include <asm/mpspec.h>
#include <asm/tables.h>
#include <asm/arch/iomap.h>
void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
void *dsdt)
{
struct acpi_table_header *header = &(fadt->header);
u16 pmbase = ACPI_PM1_BASE_ADDRESS;
memset((void *)fadt, 0, sizeof(struct acpi_fadt));
acpi_fill_header(header, "FACP");
header->length = sizeof(struct acpi_fadt);
header->revision = 4;
fadt->firmware_ctrl = (u32)facs;
fadt->dsdt = (u32)dsdt;
fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
fadt->sci_int = 9;
fadt->smi_cmd = 0;
fadt->acpi_enable = 0;
fadt->acpi_disable = 0;
fadt->s4bios_req = 0;
fadt->pstate_cnt = 0;
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = pmbase + 0x4;
fadt->pm1b_cnt_blk = 0x0;
fadt->pm2_cnt_blk = 0x0;
fadt->pm_tmr_blk = pmbase + 0x8;
fadt->gpe0_blk = ACPI_GPE0_BASE_ADDRESS;
fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 0;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0x00;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES;
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
ACPI_FADT_PLATFORM_CLOCK;
fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->reset_reg.addrl = IO_PORT_RESET;
fadt->reset_reg.addrh = 0;
fadt->reset_value = SYS_RST | RST_CPU;
fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.access_size = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.access_size = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = table_compute_checksum(fadt, header->length);
}
static int acpi_create_madt_irq_overrides(u32 current)
{
struct acpi_madt_irqoverride *irqovr;
u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
int length = 0;
irqovr = (void *)current;
length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
irqovr = (void *)(current + length);
length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
return length;
}
u32 acpi_fill_madt(u32 current)
{
current += acpi_create_madt_lapics(current);
current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
current += acpi_create_madt_irq_overrides(current);
return current;
}
......@@ -108,4 +108,4 @@ Device (prefix_ ## 0 ## func_) \
}
/* SoC specific PIRQ route configuration */
#include "irqroute.h"
#include <asm/arch/acpi/irqroute.h>
......@@ -7,26 +7,19 @@
* SPDX-License-Identifier: GPL-2.0+
*/
Scope (\)
{
/* Intel Legacy Block */
OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Field(ILBS, AnyAcc, NoLock, Preserve) {
Offset (0x8),
PRTA, 8,
PRTB, 8,
PRTC, 8,
PRTD, 8,
PRTE, 8,
PRTF, 8,
PRTG, 8,
PRTH, 8,
Offset (0x88),
, 3,
UI3E, 1,
UI4E, 1
}
}
/*
* Intel chipset PIRQ routing control ASL description
*
* The programming interface is common to most Intel chipsets. But the PRTx
* registers may be mapped to different blocks. Some chipsets map them to LPC
* device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
* some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
* Block (ILB) memory space.
*
* This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
* PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
* defined somewhere else in the platform's ASL files.
*/
Device (LNKA)
{
......
......@@ -10,6 +10,27 @@
/* Intel LPC Bus Device - 0:1f.0 */
Scope (\)
{
/* Intel Legacy Block */
OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Field(ILBS, AnyAcc, NoLock, Preserve) {
Offset (0x8),
PRTA, 8,
PRTB, 8,
PRTC, 8,
PRTD, 8,
PRTE, 8,
PRTF, 8,
PRTG, 8,
PRTH, 8,
Offset (0x88),
, 3,
UI3E, 1,
UI4E, 1
}
}
Device (LPCB)
{
Name(_ADR, 0x001f0000)
......@@ -23,7 +44,7 @@ Device (LPCB)
Offset(0x84)
}
#include "irqlinks.asl"
#include <asm/acpi/irqlinks.asl>
/* Firmware Hub */
Device (FWH)
......
......@@ -207,5 +207,5 @@ Device (PCI0)
#include "xhci.asl"
/* IRQ routing for each PCI device */
#include "irqroute.asl"
#include <asm/acpi/irqroute.asl>
}
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/device.h>
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
#define PCIE_BRIDGE_IRQ_ROUTES \
PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Intel LPC Bus Device - 0:1f.0 */
Device (LPCB)
{
Name(_ADR, 0x001f0000)
OperationRegion(PRTX, PCI_Config, 0x60, 8)
Field(PRTX, AnyAcc, NoLock, Preserve) {
PRTA, 8,
PRTB, 8,
PRTC, 8,
PRTD, 8,
PRTE, 8,
PRTF, 8,
PRTG, 8,
PRTH, 8,
}
#include <asm/acpi/irqlinks.asl>
/* Firmware Hub */
Device (FWH)
{
Name(_HID, EISAID("INT0800"))
Name(_CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
})
}
/* 8259 Interrupt Controller */
Device (PIC)
{
Name(_HID, EISAID("PNP0000"))
Name(_CRS, ResourceTemplate()
{
IO(Decode16, 0x20, 0x20, 0x01, 0x02)
IO(Decode16, 0x24, 0x24, 0x01, 0x02)
IO(Decode16, 0x28, 0x28, 0x01, 0x02)
IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
IO(Decode16, 0x30, 0x30, 0x01, 0x02)
IO(Decode16, 0x34, 0x34, 0x01, 0x02)
IO(Decode16, 0x38, 0x38, 0x01, 0x02)
IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
IO(Decode16, 0xac, 0xac, 0x01, 0x02)
IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
IRQNoFlags () { 2 }
})
}
/* 8254 timer */
Device (TIMR)
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
{
IO(Decode16, 0x40, 0x40, 0x01, 0x04)
IO(Decode16, 0x50, 0x50, 0x10, 0x04)
IRQNoFlags() { 0 }
})
}
/* HPET */
Device (HPET)
{
Name(_HID, EISAID("PNP0103"))
Name(_CID, 0x010CD041)
Name(_CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
})
Method(_STA)
{
Return (STA_VISIBLE)
}
}
/* Real Time Clock */
Device (RTC)
{
Name(_HID, EISAID("PNP0B00"))
Name(_CRS, ResourceTemplate()
{
IO(Decode16, 0x70, 0x70, 1, 8)
IRQNoFlags() { 8 }
})
}
/* LPC device: Resource consumption */
Device (LDRC)
{
Name(_HID, EISAID("PNP0C02"))
Name(_UID, 2)
Name(RBUF, ResourceTemplate()
{
IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
})
Method(_CRS, 0, NotSerialized)
{
Return (RBUF)
}
}
}
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/acpi/statdef.asl>
#include <asm/arch/iomap.h>
#include <asm/arch/irq.h>
/*
* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0.
*/
Method(_PTS, 1)
{
}
/* The _WAK method is called on system wakeup */
Method(_WAK, 1)
{
Return (Package() {0, 0})
}
/* TODO: add CPU ASL support */
Scope (\_SB)
{
#include "southcluster.asl"
}
/* Chipset specific sleep states */
#include "sleepstates.asl"
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
Device (PCI0)
{
Name(_HID, EISAID("PNP0A08")) /* PCIe */
Name(_CID, EISAID("PNP0A03")) /* PCI */
Name(_ADR, 0)
Name(_BBN, 0)
Name(MCRS, ResourceTemplate()
{
/* Bus Numbers */
WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
/* IO Region 0 */
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
/* PCI Config Space */
IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
/* IO Region 1 */
WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
/* VGA memory (0xa0000-0xbffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
0x00020000, , , ASEG)
/* OPROM reserved (0xc0000-0xc3fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
0x00004000, , , OPR0)
/* OPROM reserved (0xc4000-0xc7fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
0x00004000, , , OPR1)
/* OPROM reserved (0xc8000-0xcbfff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
0x00004000, , , OPR2)
/* OPROM reserved (0xcc000-0xcffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
0x00004000, , , OPR3)
/* OPROM reserved (0xd0000-0xd3fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
0x00004000, , , OPR4)
/* OPROM reserved (0xd4000-0xd7fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
0x00004000, , , OPR5)
/* OPROM reserved (0xd8000-0xdbfff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
0x00004000, , , OPR6)
/* OPROM reserved (0xdc000-0xdffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
0x00004000, , , OPR7)
/* BIOS Extension (0xe0000-0xe3fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
0x00004000, , , ESG0)
/* BIOS Extension (0xe4000-0xe7fff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
0x00004000, , , ESG1)
/* BIOS Extension (0xe8000-0xebfff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
0x00004000, , , ESG2)
/* BIOS Extension (0xec000-0xeffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000ec000, 0x000effff, 0x00000000,
0x00004000, , , ESG3)
/* System BIOS (0xf0000-0xfffff) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000, , , FSEG)
/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, , , PMEM)
})
Method(_CRS, 0, Serialized)
{
/* Update PCI resource area */
CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
/*
* Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h)
*
* TODO: for generic usage, read TOLM value from register, or
* from global NVS (not implemented by U-Boot yet).
*/
Store(0x80000000, PMIN)
Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
Add(Subtract(PMAX, PMIN), 1, PLEN)
Return (MCRS)
}
/* Device Resource Consumption */
Device (PDRC)
{
Name(_HID, EISAID("PNP0C02"))
Name(_UID, 1)
Name(PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000)
Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE)
IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE)
IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE)
})
/* Current Resource Settings */
Method(_CRS, 0, Serialized)
{
Return (PDRS)
}
}
Method(_OSC, 4)
{
/* Check for proper GUID */
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
/* Let OS control everything */
Return (Arg3)
} Else {
/* Unrecognized UUID */
CreateDWordField(Arg3, 0, CDW1)
Or(CDW1, 4, CDW1)
Return (Arg3)
}
}
/* LPC Bridge 0:1f.0 */
#include "lpc.asl"
/* IRQ routing for each PCI device */
#include <asm/acpi/irqroute.asl>
}
......@@ -7,12 +7,17 @@
#ifndef _QUARK_DEVICE_H_
#define _QUARK_DEVICE_H_
#include <pci.h>
/*
* Internal PCI device numbers within the SoC.
*
* Note it must start with 0x_ prefix, as the device number macro will be
* included in the ACPI ASL files (see irq_helper.h and irq_route.h).
*/
#define QUARK_HOST_BRIDGE_DEV 0
#define QUARK_HOST_BRIDGE_DEV 0x00
#define QUARK_HOST_BRIDGE_FUNC 0
#define QUARK_DEV_20 20
#define QUARK_DEV_20 0x14
#define QUARK_MMC_SDIO_FUNC 0
#define QUARK_UART0_FUNC 1
#define QUARK_USB_DEVICE_FUNC 2
......@@ -22,18 +27,21 @@
#define QUARK_EMAC0_FUNC 6
#define QUARK_EMAC1_FUNC 7
#define QUARK_DEV_21 21
#define QUARK_DEV_21 0x15
#define QUARK_SPI0_FUNC 0
#define QUARK_SPI1_FUNC 1
#define QUARK_I2C_GPIO_FUNC 2
#define QUARK_DEV_23 23
#define QUARK_DEV_23 0x17
#define QUARK_PCIE0_FUNC 0
#define QUARK_PCIE1_FUNC 1
#define QUARK_LGC_BRIDGE_DEV 31
#define QUARK_LGC_BRIDGE_DEV 0x1f
#define QUARK_LGC_BRIDGE_FUNC 0
#ifndef __ASSEMBLY__
#include <pci.h>
#define QUARK_HOST_BRIDGE \
PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC)
#define QUARK_MMC_SDIO \
......@@ -64,5 +72,6 @@
PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC)
#define QUARK_LEGACY_BRIDGE \
PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC)
#endif /* __ASSEMBLY__ */
#endif /* _QUARK_DEVICE_H_ */
/*
* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _QUARK_IOMAP_H_
#define _QUARK_IOMAP_H_
/* Memory Mapped IO bases */
/* ESRAM */
#define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE
#define ESRAM_BASE_SIZE ESRAM_SIZE
/* PCI Configuration Space */
#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
#define MCFG_BASE_SIZE 0x10000000
/* High Performance Event Timer */
#define HPET_BASE_ADDRESS 0xfed00000
#define HPET_BASE_SIZE 0x400
/* Root Complex Base Address */
#define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE
#define RCBA_BASE_SIZE 0x4000
/* IO Port bases */
#define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE
#define ACPI_PM1_BASE_SIZE 0x10
#define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE
#define ACPI_PBLK_BASE_SIZE 0x10
#define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE
#define SPI_DMA_BASE_SIZE 0x10
#define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE
#define GPIO_BASE_SIZE 0x80
#define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE
#define ACPI_GPE0_BASE_SIZE 0x40
#define WDT_BASE_ADDRESS CONFIG_WDT_BASE
#define WDT_BASE_SIZE 0x40