Commit 79048d48 authored by Ji Luo's avatar Ji Luo

imx8mq: Add support for AIY 1G ddr board

TEE will be loaded to 0x7e000000 for AIY 1G ddr board,
distinguish different baseboard by the board id and set
different tee address accordingly.

Test: build and boot ok for both AIY 1G and 3G ddr board.
Signed-off-by: default avatarJi Luo <ji.luo@nxp.com>
parent ae126e71
......@@ -85,6 +85,14 @@ static struct rdc_mda_conf masters_config[] = {
};
#endif
#ifdef SPD_trusty
#define AIY_MICRON_3G 0x1
#define AIY_MICRON_1G 0x5
#define AIY_HYNIX_1G 0x3
int get_imx8m_baseboard_id(void);
unsigned long tee_base_address;
#endif
/* set RDC settings */
static void bl31_imx_rdc_setup(void)
......@@ -209,6 +217,20 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
static console_uart_t console;
#endif
uint32_t sm_cmd;
#ifdef SPD_trusty
int board_id;
board_id = get_imx8m_baseboard_id();
if (board_id == AIY_MICRON_1G ||
board_id == AIY_HYNIX_1G) {
tee_base_address = (unsigned long)0x7e000000;
} else {
tee_base_address = (unsigned long)0xfe000000;
}
#endif
#if !defined (CSU_RDC_TEST)
int i;
/* enable CSU NS access permission */
......@@ -305,6 +327,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
#ifdef SPD_trusty
bl32_image_ep_info.args.arg0 = BL32_SIZE;
bl32_image_ep_info.args.arg1 = BL32_BASE;
/* Pass TEE base and size to uboot */
bl33_image_ep_info.args.arg1 = BL32_BASE;
#else
/* Pass TEE base and size to uboot */
bl33_image_ep_info.args.arg1 = 0xFE000000;
......
/*
* Copyright 2019 NXP
*
*/
#include <mmio.h>
#ifdef SPD_trusty
#define GPIO1_BASE_ADDR 0X30200000
#define GPIO2_BASE_ADDR 0x30210000
#define GPIO3_BASE_ADDR 0x30220000
#define GPIO4_BASE_ADDR 0x30230000
#define GPIO5_BASE_ADDR 0x30240000
/* layout of baseboard id */
#define IMX8MQ_GPIO3_IO24 88 //board_id[2]:2
#define IMX8MQ_GPIO3_IO22 86 //board_id[2]:1
#define IMX8MQ_GPIO3_IO19 83 //board_id[2]:0
struct gpio_regs {
unsigned int gpio_dr; /* data */
unsigned int gpio_dir; /* direction */
unsigned int gpio_psr; /* pad satus */
};
/* GPIO port description */
static unsigned long imx8m_gpio_ports[] = {
[0] = GPIO1_BASE_ADDR,
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
[3] = GPIO4_BASE_ADDR,
[4] = GPIO5_BASE_ADDR,
};
static int gpio_direction_input_legacy(unsigned int gpio)
{
unsigned int port;
struct gpio_regs *regs;
unsigned int l;
port = gpio/32;
gpio &= 0x1f;
regs = (struct gpio_regs *)imx8m_gpio_ports[port];
l = mmio_read_32((unsigned long)&regs->gpio_dir);
/* set direction as input. */
l &= ~(1 << gpio);
mmio_write_32((unsigned long)&regs->gpio_dir, l);
return 0;
}
static int gpio_get_value_legacy(unsigned gpio)
{
unsigned int port;
struct gpio_regs *regs;
unsigned int val;
port = gpio/32;
gpio &= 0x1f;
regs = (struct gpio_regs *)imx8m_gpio_ports[port];
val = (mmio_read_32((unsigned long)&regs->gpio_dr) >> gpio) & 0x01;
return val;
}
int get_imx8m_baseboard_id(void)
{
int i = 0, value = 0;
int baseboard_id;
int pin[3];
/* initialize the pin array */
pin[0] = IMX8MQ_GPIO3_IO19;
pin[1] = IMX8MQ_GPIO3_IO22;
pin[2] = IMX8MQ_GPIO3_IO24;
/* Set gpio direction as input and get the input value */
baseboard_id = 0;
for (i = 0; i < 3; i++) {
gpio_direction_input_legacy(pin[i]);
if ((value = gpio_get_value_legacy(pin[i])) < 0) {
return -1;
} else
baseboard_id |= ((value & 0x01) << i);
}
return baseboard_id;
}
#endif /* SPD_trusty */
......@@ -31,10 +31,13 @@
#define BL31_BASE 0x910000
#define BL31_LIMIT 0x920000
#define BL32_BASE 0xfe000000
#ifdef SPD_trusty
#define BL32_SIZE 0x02000000
#define BL32_LIMIT 0x100000000
#define BL32_BASE tee_base_address
#else
#define BL32_BASE 0xfe000000
#endif
/* non-secure uboot base */
......
......@@ -24,6 +24,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \
plat/imx/common/imx8_sip_svc.c \
plat/imx/common/misc.c \
plat/imx/imx8mq/imx8mq_psci.c \
plat/imx/imx8mq/imx8mq_gpio.c \
plat/imx/common/imx8m/imx_csu.c \
plat/imx/common/imx8m/imx_rdc.c \
plat/imx/common/imx8_topology.c \
......
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