On imx8mq B0 DRAM PLL bypass is not supported due to erratas. Report
this information upwards so that OS freq switch code doesn't mistakenly
disable DRAM pll.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>

Secure EL3 interrupt can NOT be directly trapped from secure EL1,
TEE must be aware of such interrupts.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

The parent indices can be used by an OS which manages source clocks to
enable them ahead of frequency switching.

This information is currently hardcoded but this API allows adding new
frequencies without matching changes in OS.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Jacky Bai <ping.bai@nxp.com>

This allows returning multiple parameters.

No functional change intended.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Jacky Bai <ping.bai@nxp.com>

using INTR_TYPE_EL3 SGI8 for DDR DVFS IPI interrupts.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

SC_R_GIC_SMMU is a master resource, we can't set peripheral
permission to this resource, otherwise the API will return below error
on latest SCFW, because SCFW has added a resource type check.
On old SCFW, the API does nothing to a master resource. So remove the
resource from ns_access_allowed array.

ERROR: sc_rm_set_peripheral_permissions: rsrc 14, ret 3
Signed-off-by: Ye Li <ye.li@nxp.com>

Open the power domain of MU4 and assign it to secure
world so trusty can call the SCFW API.

Test: Get SCFW and SECO-FW by trusty.

Change-Id: I6188f905426fd66072346089505fb1945e4362e3
Signed-off-by: Ji Luo <ji.luo@nxp.com>

Assign the Corresponding console uart to A core
& M domain to make sure the console is still
active when the opposite domain is in LPM mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

NOC power down will trigger the RDC memory regions reload
if any of the region is eabled.The GPU bus and DDRMIX clock
must be enable during the RDC memory region config reload
stage.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

These values are board specific so expose them to OS to reduce
duplication.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>

Return the standard SMC_UNK if x1 has an unexpected argument.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

if NOC power down is enabled in DSM mode, when system resume
back, RDC need to reload the memory regions config into the
MRCs, so PCIE, DDR, GPU bus related clock must on to make
sure RDC MRCs can be successfully reloaded.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Updating the CPU CORE power up timing to make sure
the RDC reload is done before CPU start to run code
in OCRAM space.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Updating the CPU CORE power up timing to make sure
the RDC reload is done before CPU start to run code
in OCRAM space.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Load Trusty OS from 0xBE000000. Set Trusty OS
memory base and memory space information for u-boot.

Change-Id: I13a52e176dd1e9866eb173f1c1441ba429b67acd
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>

Explict memory barrier(DSB) is necessary to make sure
other cores observe the correct flags updated by the primary
core before the primary begins doing DRAM DVFS.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

This reverts commit 58fc5c73.

The NOC power down is skipped by mistake before, so fix it.
Additionally, the OCRAM memory region protection is enabled
by ROM, but does NOT disable it. it should be disabled by
default. if there are requirments for RDC memory region
protection for OCRAM space, we can reconfigure it and enable
it again.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

This reverts commit 160e4141.

when PLAT(SCU) domain power down is enabled in
WAIT or STOP mode. enable RBC by default to make
sure SCU can be power down successfully even if
the wakeup IRQ is pending.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Since 'bus_blk_clk_rst' and 'bus_blk_clk_en' reset lines
are shared by each module in DISPMIX, so they are better
to be handled in power domain function of ATF. And other
reset lines are exclusively used by each module, so they
are better to be handled in Linux kernel drivers.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>

Since 'bus_blk_rstn' and 'bus_blk_clk_en' reset lines are
shared by each module in DISPMIX, so they are better to be
handled in power domain function of ATF. And other reset
lines are exclusively used by each module, so they are
better to be handled in Linux kernel drivers.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>

As the system is not stable when SCU power down is enabled in
WAIT mode, so just disbale it at present. Will enable it again
when finding out the root cause.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Specify the tee addr to 0xbe00_0000 for 2GB ddr AIY board.
Remove some logs for trusty to save some memory or build
will fail because of very limited ocram size on imx8mq.

Test: build and boot on AIY 2GB board.

Change-Id: I06d93857188cdda4829ad1f452755559af3983fe
Signed-off-by: Ji Luo <ji.luo@nxp.com>

Enable NOC power down in DSM by default on i.MX8MN.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Enable the D-cache early config by default. As
there is not external exclusive monitor support
for OCRAM space, so if spin lock is used in the
early resume stage, it will lead to cache coherancy
issue. So add this config to make sure spin lock
can be used safely.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

The offset of the gpc_saved_imrs was computed wrong.
Now, the offset is consistent between saving and restoring.

Fixes: 0df4c895 ("plat: imx8mq: gpc: Add array for cores IMR offset")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>

This new workaround takes advantage of the per core IMR registers in GPC in
order to unmask the IRQ0, still generated by the 12bit in IOMUX_GPR register
(which now remains always set), so it can only wake up one core at the time.
Also, this entire workaround has now been moved here in TF-A, allowing the
kernel side to be minimal.

Another advantage this workaround brings is the removal of the 50us delay
(which was necessary before in gic_raise_softirq in kernel) by allowing the
core that is waking up to mask his own IRQ0 in the suspend finish callback.

One important change here is the way the cores are woken up in
dram_dvfs_handler. Since the wake up mechanism has changed from asserting the
12th bit in IOMUX_GPR and leaving the IMR1 1st bit on for each core to exactly
the reverse, that is, leaving the IOMUX_GPR 12th bit always set and then
masking/unmasking the IMR1 1st bit for each independent core, we need to use
the imx_gpc_core_wake to wake up the cores.

Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off) from kernel
(gic_raise_softirq), since the new cpuidle workaround does not need it in order
to clean the IOMUX_GPC 12bit. For now, the udelay seems to be still needed
in order to delay the affinity info OFF for the dying core. This is something
that needs further investigation.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>

on i.MX8MN, use the 'CPU_WAIT' to check if the
M7 core is enabled or not, as M7 is always enabled
in SRC.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Add the basic support for i.MX8MN.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>

Spinlocks are added to independently safeguard concurrent
access to each core IMRs. This will be usefull later on when the masking of
the IRQ0 will be added for independent core wakeup.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Refactor the IMR access by adding arrays that hold the offsets of the first IMR
register for each core. This allows multi accesses to IMR registers for
different cores to be rolled up in a loop.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Add some delay to make sure the VPU related domain has been reset
successfully.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

the GPC set wake code can be removed. after
GICv3 driver add the necessary flags by community,
We can get all the wakeup IRQ info correctly from GIC.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Add system_reset2 support for i.MX8QM/i.MX8QX to support
WARM/COLD/BOARD reset.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

This patch updates SCFW API to v1.7, based on below commit:

252281d48647 ("SCF-105: Update wiki.")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

This patch fix type mismatch and dead codes in gpio functions.

Test: build and boot on AIY 1G DDR board.
Signed-off-by: Ji Luo <ji.luo@nxp.com>

TEE will be loaded to 0x7e000000 for AIY 1G ddr board,
distinguish different baseboard by the board id and set
different tee address accordingly.

Test: build and boot ok for both AIY 1G and 3G ddr board.
Signed-off-by: Ji Luo <ji.luo@nxp.com>

Fix the ddr4 retention exit hang caused by improper
init flow.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>