1. 30 Sep, 2019 1 commit
  2. 06 Jun, 2019 1 commit
  3. 31 May, 2019 2 commits
    • Abel Vesa's avatar
      plat: imx8mq: gpc: Fix the gpc_saved_imrs offset for pdn · 9951e98e
      Abel Vesa authored
      The offset of the gpc_saved_imrs was computed wrong.
      Now, the offset is consistent between saving and restoring.
      
      Fixes: 0df4c895 ("plat: imx8mq: gpc: Add array for cores IMR offset")
      Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
      Reviewed-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
      9951e98e
    • Abel Vesa's avatar
      MLK-21399 plat: imx8mq: gpc: Workaround for ERR11171 · 0e91ff59
      Abel Vesa authored
      This new workaround takes advantage of the per core IMR registers in GPC in
      order to unmask the IRQ0, still generated by the 12bit in IOMUX_GPR register
      (which now remains always set), so it can only wake up one core at the time.
      Also, this entire workaround has now been moved here in TF-A, allowing the
      kernel side to be minimal.
      
      Another advantage this workaround brings is the removal of the 50us delay
      (which was necessary before in gic_raise_softirq in kernel) by allowing the
      core that is waking up to mask his own IRQ0 in the suspend finish callback.
      
      One important change here is the way the cores are woken up in
      dram_dvfs_handler. Since the wake up mechanism has changed from asserting the
      12th bit in IOMUX_GPR and leaving the IMR1 1st bit on for each core to exactly
      the reverse, that is, leaving the IOMUX_GPR 12th bit always set and then
      masking/unmasking the IMR1 1st bit for each independent core, we need to use
      the imx_gpc_core_wake to wake up the cores.
      
      Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off) from kernel
      (gic_raise_softirq), since the new cpuidle workaround does not need it in order
      to clean the IOMUX_GPC 12bit. For now, the udelay seems to be still needed
      in order to delay the affinity info OFF for the dying core. This is something
      that needs further investigation.
      Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
      Reviewed-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
      0e91ff59
  4. 29 May, 2019 1 commit
  5. 28 May, 2019 1 commit
  6. 27 May, 2019 2 commits
  7. 22 May, 2019 1 commit
  8. 13 May, 2019 1 commit
  9. 19 Apr, 2019 1 commit
  10. 08 Apr, 2019 1 commit
  11. 01 Apr, 2019 2 commits
  12. 21 Mar, 2019 1 commit
  13. 14 Mar, 2019 1 commit
  14. 13 Mar, 2019 1 commit
  15. 12 Mar, 2019 2 commits
  16. 05 Mar, 2019 1 commit
  17. 04 Mar, 2019 1 commit
  18. 27 Feb, 2019 6 commits
  19. 26 Feb, 2019 1 commit
  20. 20 Feb, 2019 1 commit
  21. 15 Feb, 2019 1 commit
  22. 12 Feb, 2019 2 commits
    • Anson Huang's avatar
      gic: make sure ProcessorSleep bit clear successfully · 4436f3a4
      Anson Huang authored
      GICR_WAKER.ProcessorSleep can only be set to zero when:
      — GICR_WAKER.Sleep bit[0] == 0.
      — GICR_WAKER.Quiescent bit[31] == 0.
      
      On some platforms, when system reboot with GIC in sleep
      mode but with power ON, such as on NXP's i.MX8QM, Linux
      kernel enters suspend but could be requested to reboot,
      and GIC is in sleep mode and it is inside a power domain
      which is ON in this scenario, when CPU reset, the GIC
      driver trys to set CORE's redistributor interface to awake,
      with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31]
      both set, the ProcessorSleep bit[1] will never be clear
      and cause system hang.
      
      This patch makes sure GICR_WAKER.Sleep bit[0] and
      GICR_WAKER.Quiescent bit[31] are both zeor before clearing
      ProcessorSleep bit[1].
      Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      4436f3a4
    • Haoran.Wang's avatar
      MA-13239 imx8qm: Touch correct pad for UART0 · 21c05ef1
      Haoran.Wang authored
      Due imx8qm_mek's UART0_RTS_B and UART0_CTS_0 pad
      reuse to be the UART2 for base bard which operated by
      M4_1, so don't touch these two pads in ATF.
      Signed-off-by: default avatarHaoran.Wang <elven.wang@nxp.com>
      Acked-by: default avatarPete Zhang <pete.zhang@nxp.com>
      21c05ef1
  23. 11 Feb, 2019 2 commits
    • Anson Huang's avatar
      imx: enable IRQ steer wakeup source support · 854729ba
      Anson Huang authored
      Enable IRQ steer wakeup source support for Linux kernel
      wakeup sources like debug UART wakeup etc..
      Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      854729ba
    • Ye Li's avatar
      imx8qm/qxp: Protect the lower 96K ocram used for SPL · 96d33120
      Ye Li authored
      Because the partition reboot won't reload the first level bootloader (SPL),
      the SPL won't be authenticated. Users can corrupt the SPL image to break
      the boot trust chain in secure boot if we don't protect that OCRAM area.
      
      This patch configures the memory area from 0x0 to 0x118000 only accessed by
      secure partition (ATF and OPTEE). Non-secure partitions (u-boot and kernel)
      can't access it.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 1eff7d3ef6f121782e56bb1807744ede48b8580b)
      96d33120
  24. 10 Feb, 2019 1 commit
  25. 07 Feb, 2019 5 commits