Commit 195c0283 authored by Jacky Bai's avatar Jacky Bai

plat: imx8mn: Add the basic support for imx8mn

Add the basic support for i.MX8MN.
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarYe Li <ye.li@nxp.com>
parent 60492955
......@@ -34,7 +34,7 @@ uintptr_t imx_svc_smc_handler(uint32_t smc_fid,
u_register_t flags)
{
switch (smc_fid) {
#if defined(PLAT_IMX8M) || defined(PLAT_IMX8MM)
#if defined(PLAT_IMX8M) || defined(PLAT_IMX8MM) || defined(PLAT_IMX8MN)
case FSL_SIP_DDR_DVFS:
SMC_RET1(handle, dram_dvfs_handler(smc_fid, x1, x2, x3));
break;
......
......@@ -80,7 +80,7 @@ int imx_misc_set_temp_handler(uint32_t smc_fid, u_register_t x1,
u_register_t x4);
#endif
#if defined(PLAT_IMX8M) || defined(PLAT_IMX8MM)
#if defined(PLAT_IMX8M) || defined(PLAT_IMX8MM) || defined(PLAT_IMX8MN)
int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
u_register_t x2, u_register_t x3);
int lpddr4_dvfs_handler(uint32_t smc_fid, u_register_t x1,
......
This diff is collapsed.
/*
* Copyright 2019 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <context.h>
#include <context_mgmt.h>
#include <debug.h>
#include <stdbool.h>
#include <dram.h>
#include <generic_delay_timer.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
#include <plat_imx8.h>
#include <xlat_tables.h>
#include <soc.h>
#include <tzc380.h>
#include <imx_csu.h>
#include <imx_rdc.h>
#include <uart.h>
/* linker defined symbols */
IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START);
IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END);
IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
#define CAAM_BASE (0x30900000) /* HW address*/
#define JR0_BASE (CAAM_BASE + 0x1000)
#define CAAM_JR0MID (0x30900010)
#define CAAM_JR1MID (0x30900018)
#define CAAM_JR2MID (0x30900020)
#define CAAM_NS_MID (0x1)
#define SM_P0_PERM (JR0_BASE + 0xa04)
#define SM_P0_SMAG2 (JR0_BASE + 0xa08)
#define SM_P0_SMAG1 (JR0_BASE + 0xa0c)
#define SM_CMD (JR0_BASE + 0xbe4)
/* secure memory command */
#define SMC_PAGE_SHIFT 16
#define SMC_PART_SHIFT 8
#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */
#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
/* get SPSR for BL33 entry */
static uint32_t get_spsr_for_bl33_entry(void)
{
unsigned long el_status;
unsigned long mode;
uint32_t spsr;
/* figure out what mode we enter the non-secure world */
el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
el_status &= ID_AA64PFR0_ELX_MASK;
mode = (el_status) ? MODE_EL2 : MODE_EL1;
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
#define SCTR_BASE_ADDR 0x306c0000
#define CNTFID0_OFF 0x20
#define CNTFID1_OFF 0x24
#define SC_CNTCR_ENABLE (1 << 0)
#define SC_CNTCR_HDBG (1 << 1)
#define SC_CNTCR_FREQ0 (1 << 8)
#define SC_CNTCR_FREQ1 (1 << 9)
#define GPR_TZASC_EN (1 << 0)
#define GPR_TZASC_EN_LOCK (1 << 16)
void bl31_tzc380_setup(void)
{
unsigned int val;
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
return;
NOTICE("Configuring TZASC380\n");
tzc380_init(IMX_TZASC_BASE);
/*
* Need to substact offset 0x40000000 from CPU address when
* programming tzasc region for i.mx8mq.
*/
/* Enable 1G-5G S/NS RW */
tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G)
| TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
}
static void imx8mn_caam_config(void)
{
uint32_t sm_cmd;
/* Dealloc part 0 and 2 with current DID */
sm_cmd = (0 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
mmio_write_32(SM_CMD, sm_cmd);
sm_cmd = (2 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
mmio_write_32(SM_CMD, sm_cmd);
/* config CAAM JRaMID set MID to Cortex A */
mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
mmio_write_32(CAAM_JR2MID, CAAM_NS_MID);
/* Alloc partition 0 writing SMPO and SMAGs */
mmio_write_32(SM_P0_PERM, 0xff);
mmio_write_32(SM_P0_SMAG2, 0xffffffff);
mmio_write_32(SM_P0_SMAG1, 0xffffffff);
/* Allocate page 0 and 1 to partition 0 with DID set */
sm_cmd = (0 << SMC_PAGE_SHIFT
| 0 << SMC_PART_SHIFT
| SMC_CMD_ALLOC_PAGE);
mmio_write_32(SM_CMD, sm_cmd);
sm_cmd = (1 << SMC_PAGE_SHIFT
| 0 << SMC_PART_SHIFT
| SMC_CMD_ALLOC_PAGE);
mmio_write_32(SM_CMD, sm_cmd);
}
static void imx8mn_aips_config(void)
{
/* config the AIPSTZ1 */
mmio_write_32(0x301f0000, 0x77777777);
mmio_write_32(0x301f0004, 0x77777777);
mmio_write_32(0x301f0040, 0x0);
mmio_write_32(0x301f0044, 0x0);
mmio_write_32(0x301f0048, 0x0);
mmio_write_32(0x301f004c, 0x0);
mmio_write_32(0x301f0050, 0x0);
/* config the AIPSTZ2 */
mmio_write_32(0x305f0000, 0x77777777);
mmio_write_32(0x305f0004, 0x77777777);
mmio_write_32(0x305f0040, 0x0);
mmio_write_32(0x305f0044, 0x0);
mmio_write_32(0x305f0048, 0x0);
mmio_write_32(0x305f004c, 0x0);
mmio_write_32(0x305f0050, 0x0);
/* config the AIPSTZ3 */
mmio_write_32(0x309f0000, 0x77777777);
mmio_write_32(0x309f0004, 0x77777777);
mmio_write_32(0x309f0040, 0x0);
mmio_write_32(0x309f0044, 0x0);
mmio_write_32(0x309f0048, 0x0);
mmio_write_32(0x309f004c, 0x0);
mmio_write_32(0x309f0050, 0x0);
/* config the AIPSTZ4 */
mmio_write_32(0x32df0000, 0x77777777);
mmio_write_32(0x32df0004, 0x77777777);
mmio_write_32(0x32df0040, 0x0);
mmio_write_32(0x32df0044, 0x0);
mmio_write_32(0x32df0048, 0x0);
mmio_write_32(0x32df004c, 0x0);
mmio_write_32(0x32df0050, 0x0);
}
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
#if DEBUG_CONSOLE
static console_uart_t console;
#endif
int i;
/* enable CSU NS access permission */
for (i = 0; i < 64; i++) {
mmio_write_32(0x303e0000 + i * 4, 0x00ff00ff);
}
/* enable the secure access only for secure OCRAM */
mmio_write_32(0x303e00ec, 0x00330033);
/* config the ocram memory for secure access */
mmio_write_32(0x3034002c, 0xc1);
/* config the aips access permission */
imx8mn_aips_config();
/* config the caam access permission */
imx8mn_caam_config();
#if DEBUG_CONSOLE
console_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
#endif
/*
* tell BL3-1 where the non-secure software image is located
* and the entry state information.
*/
bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
#ifdef TEE_IMX8
/* Populate entry point information for BL32 */
SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
bl32_image_ep_info.pc = BL32_BASE;
bl32_image_ep_info.spsr = 0;
/* Pass TEE base and size to uboot */
bl33_image_ep_info.args.arg1 = 0xBE000000;
bl33_image_ep_info.args.arg2 = 0x2000000;
#endif
bl31_tzc380_setup();
}
void bl31_plat_arch_setup(void)
{
/* add the mmap */
mmap_add_region(0x900000, 0x900000, 0x80000, MT_MEMORY | MT_RW);
mmap_add_region(0x100000, 0x100000, 0x10000, MT_MEMORY | MT_RW);
mmap_add_region(0x40000000, 0x40000000, 0xc0000000,
MT_MEMORY | MT_RW | MT_NS);
mmap_add_region(BL31_BASE, BL31_BASE, BL31_RO_END - BL31_RO_START,
MT_MEMORY | MT_RO);
mmap_add_region(IMX_ROM_BASE, IMX_ROM_BASE, 0x40000, MT_MEMORY | MT_RO);
/* Map AIPS 1~3 */
mmap_add_region(IMX_AIPS_BASE, IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW);
/* map AIPS4 */
mmap_add_region(0x32c00000, 0x32c00000, 0x400000, MT_DEVICE | MT_RW);
/* map GIC */
mmap_add_region(PLAT_GIC_BASE, PLAT_GIC_BASE, 0x100000, MT_DEVICE | MT_RW);
/* Map DDRC/PHY/PERF */
mmap_add_region(0x3c000000, 0x3c000000, 0x4000000, MT_DEVICE | MT_RW);
mmap_add_region(OCRAM_S_BASE, OCRAM_S_BASE, OCRAM_S_SIZE, MT_MEMORY | MT_RW);
#if USE_COHERENT_MEM
mmap_add_region(BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW);
#endif
/* setup xlat table */
init_xlat_tables();
/* enable the MMU */
enable_mmu_el3(0);
}
void bl31_platform_setup(void)
{
generic_delay_timer_init();
/* select the CKIL source to 32K OSC */
mmio_write_32(IMX_ANAMIX_BASE + 0x124, 0x1);
/* init the dram info */
dram_info_init(SAVED_DRAM_TIMING_BASE);
/* init the GICv3 cpu and distributor interface */
plat_gic_driver_init();
plat_gic_init();
/* gpc init */
imx_gpc_init();
/* Enable and reset M7 */
mmio_setbits_32(IMX_SRC_BASE + 0xc, 1 << 3);
mmio_clrbits_32(IMX_SRC_BASE + 0xc, 0x1);
}
entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
{
if (type == NON_SECURE)
return &bl33_image_ep_info;
if (type == SECURE)
return &bl32_image_ep_info;
return NULL;
}
unsigned int plat_get_syscnt_freq2(void)
{
return COUNTER_FREQUENCY;
}
void bl31_plat_runtime_setup(void)
{
return;
}
/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <debug.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <runtime_svc.h>
#include <std_svc.h>
#include <mmio.h>
#include <platform_def.h>
#include <imx_sip.h>
#include <soc.h>
#define DIGPROG 0x800
int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
u_register_t x3)
{
uint32_t val;
switch(x1) {
case FSL_SIP_SRC_M4_START:
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x58);
val &= ~0x1;
mmio_write_32(IMX_IOMUX_GPR_BASE + 0x58, val);
break;
case FSL_SIP_SRC_M4_STARTED:
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x58);
return !(val & 0x1);
default:
return SMC_UNK;
};
return 0;
}
int imx_soc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
u_register_t x3)
{
return mmio_read_32(IMX_ANAMIX_BASE + DIGPROG);
}
int imx_noc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
u_register_t x3)
{
return 0;
}
/*
* Copyright 2019 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include <debug.h>
#include <stdbool.h>
#include <dram.h>
#include <plat_imx8.h>
#include <psci.h>
#include <mmio.h>
#include <soc.h>
#define SNVS_LPCR 0x38
#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
int imx_pwr_domain_on(u_register_t mpidr)
{
unsigned int core_id;
uint64_t base_addr = BL31_BASE;
core_id = MPIDR_AFFLVL0_VAL(mpidr);
/* set the secure entrypoint */
imx_set_cpu_secure_entry(core_id, base_addr);
/* power up the core */
imx_set_cpu_pwr_on(core_id);
return PSCI_E_SUCCESS;
}
void imx_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
/* program the GIC per cpu dist and rdist interface */
plat_gic_pcpu_init();
/* enable the GICv3 cpu interface */
plat_gic_cpuif_enable();
}
void imx_pwr_domain_off(const psci_power_state_t *target_state)
{
uint64_t mpidr = read_mpidr_el1();
unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
/* disable the GIC cpu interface first */
plat_gic_cpuif_disable();
/* config the core for power down */
imx_set_cpu_pwr_off(core_id);
}
int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)
{
/* The non-secure entrypoint should be in RAM space */
if (ns_entrypoint < 0x40000000)
return PSCI_E_INVALID_PARAMS;
return PSCI_E_SUCCESS;
}
int imx_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
int pwr_type = psci_get_pstate_type(power_state);
int state_id = psci_get_pstate_id(power_state);
if (pwr_lvl > PLAT_MAX_PWR_LVL)
return PSCI_E_INVALID_PARAMS;
if (pwr_type == PSTATE_TYPE_STANDBY) {
CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
}
if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) {
CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE;
CLUSTER_PWR_STATE(req_state) = PLAT_WAIT_RET_STATE;
}
return PSCI_E_SUCCESS;
}
void imx_cpu_standby(plat_local_state_t cpu_state)
{
dsb();
write_scr_el3(read_scr_el3() | 0x4);
isb();
wfi();
write_scr_el3(read_scr_el3() & (~0x4));
isb();
}
void imx_domain_suspend(const psci_power_state_t *target_state)
{
uint64_t base_addr = BL31_BASE;
uint64_t mpidr = read_mpidr_el1();
unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
if (is_local_state_off(CORE_PWR_STATE(target_state))) {
/* disable the cpu interface */
plat_gic_cpuif_disable();
/* set the resume entry */
imx_set_cpu_secure_entry(core_id, base_addr);
imx_set_cpu_lpm(core_id, true);
} else {
/* TODO cluster level clock gate off ? */
dsb();
write_scr_el3(read_scr_el3() | 0x4);
isb();
}
if (!is_local_state_run(CLUSTER_PWR_STATE(target_state)))
imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state));
/* do system level power mode setting */
if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
if (!imx_is_m4_enabled() || !imx_m4_lpa_active())
dram_enter_retention();
imx_set_sys_lpm(true);
imx_anamix_pre_suspend();
noc_wrapper_pre_suspend(core_id);
/* set the wakeup source based on GIC SPI config */
imx_set_sys_wakeup(core_id, true);
}
}
void imx_domain_suspend_finish(const psci_power_state_t *target_state)
{
uint64_t mpidr = read_mpidr_el1();
unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
/* check the system level status */
if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
imx_set_sys_lpm(false);
/* clear the system wakeup setting */
imx_set_sys_wakeup(core_id, false);
imx_anamix_post_resume();
imx_clear_rbc_count();
if (!imx_is_m4_enabled() || !imx_m4_lpa_active())
dram_exit_retention();
noc_wrapper_post_resume(core_id);
}
/* check the cluster level power status */
if (!is_local_state_run(CLUSTER_PWR_STATE(target_state)))
imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN);
/* check the core level power status */
if (is_local_state_off(CORE_PWR_STATE(target_state))) {
/* clear the core lpm setting */
imx_set_cpu_lpm(core_id, false);
/* enable the gic cpu interface */
plat_gic_cpuif_enable();
} else {
write_scr_el3(read_scr_el3() & (~0x4));
isb();
}
}
void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
unsigned int i;
for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE;
}
void __dead2 imx_system_reset(void)
{
uintptr_t wdog_base = IMX_WDOG_BASE;
unsigned int val;
/* WDOG_B reset */
val = mmio_read_16(wdog_base);
#ifdef IMX_WDOG_B_RESET
val = (val & 0x00FF) | (7 << 2) | (1 << 0);
#else
val = (val & 0x00FF) | (4 << 2) | (1 << 0);
#endif
mmio_write_16(wdog_base, val);
mmio_write_16(wdog_base + 0x2, 0x5555);
mmio_write_16(wdog_base + 0x2, 0xaaaa);
while (1)
;
}
void __dead2 imx_system_off(void)
{
mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, 0x61);
INFO("Unable to poweroff system\n");
while (1)
;
}
void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
{
if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) {
imx_set_rbc_count();
}
while (1)
wfi();
}
static const plat_psci_ops_t imx_plat_psci_ops = {
.pwr_domain_on = imx_pwr_domain_on,
.pwr_domain_on_finish = imx_pwr_domain_on_finish,
.pwr_domain_off = imx_pwr_domain_off,
.validate_ns_entrypoint = imx_validate_ns_entrypoint,
.validate_power_state = imx_validate_power_state,
.cpu_standby = imx_cpu_standby,
.pwr_domain_suspend = imx_domain_suspend,
.pwr_domain_suspend_finish = imx_domain_suspend_finish,
.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
.system_reset = imx_system_reset,
.system_off = imx_system_off,
};
/* export the platform specific psci ops */
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const plat_psci_ops_t **psci_ops)
{
/* sec_entrypoint is used for warm reset */
imx_mailbox_init(sec_entrypoint);
*psci_ops = &imx_plat_psci_ops;
return 0;
}
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
#define PLATFORM_STACK_SIZE 0xB00
#define CACHE_WRITEBACK_GRANULE 64
#define PLAT_PRIMARY_CPU 0x0
#define PLATFORM_MAX_CPU_PER_CLUSTER 4
#define PLATFORM_CLUSTER_COUNT 1
#define PLATFORM_CLUSTER0_CORE_COUNT 4
#define PLATFORM_CLUSTER1_CORE_COUNT 0
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
#define IMX_PWR_LVL0 MPIDR_AFFLVL0
#define IMX_PWR_LVL1 MPIDR_AFFLVL1
#define IMX_PWR_LVL2 MPIDR_AFFLVL2
#define PWR_DOMAIN_AT_MAX_LVL 1
#define PLAT_MAX_PWR_LVL 2
#define PLAT_MAX_OFF_STATE 4
#define PLAT_MAX_RET_STATE 2
#define PLAT_WAIT_RET_STATE 1
#define PLAT_STOP_OFF_STATE 3
#define BL31_BASE 0x960000
#define BL31_LIMIT 0x980000
#define BL32_BASE 0xbe000000
/* non-secure uboot base */
#define PLAT_NS_IMAGE_OFFSET 0x40200000
/* GICv3 base address */
#define PLAT_GIC_BASE 0x38800000
#define PLAT_GICD_BASE 0x38800000
#define PLAT_GICR_BASE 0x38880000
#define PLAT_FSL_ADDR_SPACE_SIZE (1ull << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
#define MAX_XLAT_TABLES 4
#define MAX_MMAP_REGIONS 12
#define HAB_RVT_BASE 0x00000900 /* HAB_RVT for i.MX8MM */
#define IMX_BOOT_UART_BASE 0x30890000
#define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24Mhz OSC */
#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
#define PLAT_CRASH_UART_CLK_IN_HZ 24000000
#define IMX_CONSOLE_BAUDRATE 115200
#define IMX_AIPSTZ1 0x301f0000
#define IMX_AIPSTZ2 0x305f0000
#define IMX_AIPSTZ3 0x309f0000
#define IMX_AIPSTZ4 0x32df0000
#define IMX_AIPS_BASE 0x30000000
#define IMX_AIPS_SIZE 0xC00000
#define IMX_GPV_BASE 0x32000000
#define IMX_GPV_SIZE 0x800000
#define IMX_AIPS1_BASE 0x30200000
#define IMX_AIPS4_BASE 0x32c00000
#define IMX_ANAMIX_BASE 0x30360000
#define IMX_CCM_BASE 0x30380000
#define IMX_SRC_BASE 0x30390000
#define IMX_GPC_BASE 0x303a0000
#define IMX_RDC_BASE 0x303d0000
#define IMX_CSU_BASE 0x303e0000
#define IMX_WDOG_BASE 0x30280000
#define IMX_SNVS_BASE 0x30370000
#define IMX_NOC_BASE 0x32700000
#define IMX_TZASC_BASE 0x32F80000
#define IMX_IOMUX_GPR_BASE 0x30340000
#define IMX_DDRC_BASE 0x3d400000
#define IMX_DDRPHY_BASE 0x3c000000
#define IMX_DDR_IPS_BASE 0x3d000000
#define IMX_ROM_BASE 0x0
#define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50)
#define OCRAM_S_BASE 0x00180000
#define OCRAM_S_SIZE 0x8000
#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE)
#define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
#define DEBUG_CONSOLE 0
#define IMX_WDOG_B_RESET
#define PLAT_IMX8MN 1
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_SOC_H
#define __IMX_SOC_H
#include <stdbool.h>
void imx_gpc_set_m_core_pgc(unsigned int cpu, bool pdn);
void imx_anamix_pre_suspend(void);
void imx_anamix_post_resume(void);
void imx_gpc_init(void);
void imx_set_cpu_secure_entry(int cpu_id, uintptr_t sec_entrypoint);
void imx_set_cpu_pwr_off(int cpu_id);
void imx_set_cpu_pwr_on(int cpu_id);
void imx_set_cpu_lpm(int cpu_id, bool pdn);