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Librem5
arm-trusted-firmware
Commits
92c2de12
Commit
92c2de12
authored
Nov 11, 2019
by
Martin Kepplinger
Browse files
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Browse Files
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Plain Diff
Merge branch 'busfreq' into 'librem5'
Busfreq See merge request
!2
parents
b77c7f33
783fc2b2
Pipeline
#44443
passed with stage
in 36 seconds
Changes
15
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1
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15 changed files
with
265 additions
and
55 deletions
+265
-55
plat/imx/common/imx8_helpers.S
plat/imx/common/imx8_helpers.S
+29
-0
plat/imx/common/imx8_sip_svc.c
plat/imx/common/imx8_sip_svc.c
+2
-3
plat/imx/common/imx8m/dram.c
plat/imx/common/imx8m/dram.c
+108
-17
plat/imx/common/include/imx_sip.h
plat/imx/common/include/imx_sip.h
+6
-3
plat/imx/common/plat_imx8_gic.c
plat/imx/common/plat_imx8_gic.c
+1
-3
plat/imx/imx8mm/gpc.c
plat/imx/imx8mm/gpc.c
+19
-7
plat/imx/imx8mn/gpc.c
plat/imx/imx8mn/gpc.c
+33
-18
plat/imx/imx8mn/imx8mn_bl31_setup.c
plat/imx/imx8mn/imx8mn_bl31_setup.c
+33
-0
plat/imx/imx8mn/imx8mn_psci.c
plat/imx/imx8mn/imx8mn_psci.c
+14
-3
plat/imx/imx8mn/include/platform_def.h
plat/imx/imx8mn/include/platform_def.h
+10
-0
plat/imx/imx8mq/imx8mq_bl31_setup.c
plat/imx/imx8mq/imx8mq_bl31_setup.c
+6
-0
plat/imx/imx8qm/imx8qm_bl31_setup.c
plat/imx/imx8qm/imx8qm_bl31_setup.c
+1
-0
plat/imx/imx8qm/include/sec_rsrc.h
plat/imx/imx8qm/include/sec_rsrc.h
+1
-1
plat/imx/imx8qx/imx8qx_bl31_setup.c
plat/imx/imx8qx/imx8qx_bl31_setup.c
+1
-0
plat/imx/imx8qx/include/sec_rsrc.h
plat/imx/imx8qx/include/sec_rsrc.h
+1
-0
No files found.
plat/imx/common/imx8_helpers.S
View file @
92c2de12
...
...
@@ -7,6 +7,7 @@
#include <asm_macros.S>
#include <platform_def.h>
#include <cortex_a35.h>
#include <cortex_a72.h>
.
globl
plat_is_my_cpu_primary
.
globl
plat_my_core_pos
...
...
@@ -85,6 +86,34 @@ func plat_calc_core_pos
ret
endfunc
plat_calc_core_pos
/
*
----------------------------------------------
*
function
to
handle
platform
specific
reset
.
*
----------------------------------------------
*/
func
plat_reset_handler
/
*
enable
EL2
cpuectlr
RW
access
*/
mov
x0
,
#
0x73
msr
actlr_el3
,
x0
msr
actlr_el2
,
x0
isb
/
*
--------------------------------------------------------------------
*
Nothing
to
do
on
Cortex
-
A53
.
*
--------------------------------------------------------------------
*/
jump_if_cpu_midr
CORTEX_A72_MIDR
,
A72
ret
A72
:
/
*
--------------------------------------------------------------------
*
Cortex
-
A72
specific
settings
*
--------------------------------------------------------------------
*/
mov
x0
,
#(
CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES
<<
CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT
)
msr
CORTEX_A72_L2CTLR_EL1
,
x0
isb
ret
endfunc
plat_reset_handler
/
*
---------------------------------------------
*
function
to
get
the
entrypoint
.
*
---------------------------------------------
...
...
plat/imx/common/imx8_sip_svc.c
View file @
92c2de12
...
...
@@ -35,9 +35,8 @@ uintptr_t imx_svc_smc_handler(uint32_t smc_fid,
{
switch
(
smc_fid
)
{
#if defined(PLAT_IMX8M) || defined(PLAT_IMX8MM) || defined(PLAT_IMX8MN)
case
FSL_SIP_DDR_DVFS
:
SMC_RET1
(
handle
,
dram_dvfs_handler
(
smc_fid
,
x1
,
x2
,
x3
));
break
;
case
IMX_SIP_DDR_DVFS
:
return
dram_dvfs_handler
(
smc_fid
,
handle
,
x1
,
x2
,
x3
);
case
FSL_SIP_GPC
:
SMC_RET1
(
handle
,
imx_gpc_handler
(
smc_fid
,
x1
,
x2
,
x3
));
break
;
...
...
plat/imx/common/imx8m/dram.c
View file @
92c2de12
...
...
@@ -9,6 +9,11 @@
#include <dram.h>
#include <mmio.h>
#include <spinlock.h>
#include <smccc.h>
#include <smccc_helpers.h>
#include <imx_sip.h>
#include <interrupt_mgmt.h>
#include <std_svc.h>
static
struct
dram_info
dram_info
;
...
...
@@ -16,11 +21,8 @@ static struct dram_info dram_info;
spinlock_t
dfs_lock
;
/* IRQ used for DDR DVFS */
#if defined(PLAT_IMX8M)
static
uint32_t
irqs_used
[]
=
{
102
,
109
,
110
,
111
};
/* ocram used to dram timing */
static
uint8_t
dram_timing_saved
[
13
*
1024
]
__aligned
(
8
);
#else
static
uint32_t
irqs_used
[]
=
{
74
,
75
,
76
,
77
};
#endif
static
volatile
uint32_t
wfe_done
;
static
volatile
bool
wait_ddrc_hwffc_done
=
true
;
...
...
@@ -155,6 +157,35 @@ static bool is_bypass_mode_enabled(struct dram_timing_info *info)
return
true
;
}
/* EL3 SGI-8 handler */
static
uint64_t
waiting_dvfs
(
uint32_t
id
,
uint32_t
flags
,
void
*
handle
,
void
*
cookie
)
{
uint64_t
mpidr
=
read_mpidr_el1
();
unsigned
int
cpu_id
=
MPIDR_AFFLVL0_VAL
(
mpidr
);
uint32_t
irq
;
irq
=
plat_ic_acknowledge_interrupt
();
if
(
irq
<
1022U
)
{
plat_ic_end_of_interrupt
(
irq
);
}
/* set the WFE done status */
spin_lock
(
&
dfs_lock
);
wfe_done
|=
(
1
<<
cpu_id
*
8
);
dsb
();
spin_unlock
(
&
dfs_lock
);
while
(
1
)
{
/* ddr frequency change done */
wfe
();
if
(
!
wait_ddrc_hwffc_done
)
break
;
}
return
0
;
}
void
dram_info_init
(
unsigned
long
dram_timing_base
)
{
uint32_t
current_fsp
,
ddr_type
,
ddrc_mstr
;
...
...
@@ -196,6 +227,16 @@ void dram_info_init(unsigned long dram_timing_base)
dcsw_op_all
(
DCCSW
);
ddr4_swffc
(
&
dram_info
,
0x0
);
}
/* register the SGI handler for DVFS */
uint64_t
flags
=
0
;
uint64_t
rc
;
set_interrupt_rm_flag
(
flags
,
NON_SECURE
);
rc
=
register_interrupt_type_handler
(
INTR_TYPE_EL3
,
waiting_dvfs
,
flags
);
if
(
rc
)
panic
();
}
void
dram_enter_retention
(
void
)
...
...
@@ -214,7 +255,49 @@ void dram_exit_retention(void)
ddr4_exit_retention
();
}
/*
* For each freq return the following info:
*
* r1: data rate
* r2: 1 + dram_core parent
* r3: 1 + dram_alt parent index
* r4: 1 + dram_apb parent index
*
* The parent indices can be used by an OS who manages source clocks to enabled
* them ahead of the switch.
*
* A parent value of "0" means "don't care".
*
* Current implementation of freq switch is hardcoded in
* plat/imx/common/imx8m/clock.c but in theory this can be enhanced to support
* a wide variety of rates.
*/
int
dram_dvfs_get_freq_info
(
void
*
handle
,
u_register_t
index
)
{
switch
(
index
)
{
case
0
:
SMC_RET4
(
handle
,
dram_info
.
timing_info
->
fsp_table
[
0
],
1
,
0
,
5
);
case
1
:
if
(
!
bypass_mode_supported
)
SMC_RET4
(
handle
,
dram_info
.
timing_info
->
fsp_table
[
1
],
1
,
0
,
0
);
SMC_RET4
(
handle
,
dram_info
.
timing_info
->
fsp_table
[
1
],
2
,
2
,
4
);
case
2
:
if
(
!
bypass_mode_supported
)
SMC_RET4
(
handle
,
dram_info
.
timing_info
->
fsp_table
[
2
],
1
,
0
,
0
);
SMC_RET4
(
handle
,
dram_info
.
timing_info
->
fsp_table
[
2
],
2
,
3
,
3
);
case
3
:
SMC_RET4
(
handle
,
dram_info
.
timing_info
->
fsp_table
[
3
],
1
,
0
,
0
);
default:
SMC_RET1
(
handle
,
-
3
);
}
}
int
dram_dvfs_handler
(
uint32_t
smc_fid
,
void
*
handle
,
u_register_t
x1
,
u_register_t
x2
,
u_register_t
x3
)
...
...
@@ -224,36 +307,42 @@ int dram_dvfs_handler(uint32_t smc_fid,
unsigned
int
target_freq
=
x1
;
uint32_t
online_cores
=
x2
;
if
(
target_freq
==
0xf
)
{
if
(
x1
==
IMX_SIP_DDR_DVFS_WAIT_CHANGE
)
{
/* set the WFE done status */
spin_lock
(
&
dfs_lock
);
wfe_done
|=
(
1
<<
cpu_id
*
8
);
dsb
();
spin_unlock
(
&
dfs_lock
);
while
(
1
)
{
/* ddr frequency change done */
wfe
();
if
(
!
wait_ddrc_hwffc_done
)
{
if
(
!
wait_ddrc_hwffc_done
)
break
;
}
}
}
else
{
}
else
if
(
x1
==
IMX_SIP_DDR_DVFS_GET_FREQ_COUNT
)
{
int
i
;
for
(
i
=
0
;
i
<
4
;
++
i
)
if
(
!
dram_info
.
timing_info
->
fsp_table
[
i
])
break
;
SMC_RET1
(
handle
,
i
);
}
else
if
(
x1
==
IMX_SIP_DDR_DVFS_GET_FREQ_INFO
)
{
return
dram_dvfs_get_freq_info
(
handle
,
x2
);
}
else
if
(
x1
<
4
)
{
wait_ddrc_hwffc_done
=
true
;
/* trigger the IRQ */
for
(
int
i
=
0
;
i
<
4
;
i
++
)
{
int
irq
=
irqs_used
[
i
]
%
32
;
if
(
cpu_id
!=
i
&&
(
online_cores
&
(
0x1
<<
(
i
*
8
))))
{
mmio_write_32
(
0x38800204
+
(
irqs_used
[
i
]
/
32
)
*
4
,
(
1
<<
irq
));
}
}
dsb
();
/* trigger the SGI to info other cores */
for
(
int
i
=
0
;
i
<
PLATFORM_CORE_COUNT
;
i
++
)
if
(
cpu_id
!=
i
&&
(
online_cores
&
(
0x1
<<
(
i
*
8
))))
plat_ic_raise_el3_sgi
(
0x8
,
i
);
/* make sure all the core in WFE */
online_cores
&=
~
(
0x1
<<
(
cpu_id
*
8
));
#if defined(PLAT_IMX8M)
for
(
int
i
=
0
;
i
<
4
;
i
++
)
{
if
(
i
!=
cpu_id
&&
online_cores
&
(
1
<<
(
i
*
8
)))
{
if
(
i
!=
cpu_id
&&
online_cores
&
(
1
<<
(
i
*
8
)))
imx_gpc_core_wake
(
1
<<
i
);
}
}
#endif
while
(
1
)
{
...
...
@@ -276,7 +365,9 @@ int dram_dvfs_handler(uint32_t smc_fid,
dsb
();
sev
();
isb
();
SMC_RET1
(
handle
,
0
);
}
return
0
;
SMC_RET1
(
handle
,
SMC_UNK
)
;
}
plat/imx/common/include/imx_sip.h
View file @
92c2de12
...
...
@@ -31,7 +31,10 @@
#define IMX_SIP_BUILDINFO 0xC2000003
#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
#define FSL_SIP_DDR_DVFS 0xc2000004
#define IMX_SIP_DDR_DVFS 0xc2000004
#define IMX_SIP_DDR_DVFS_WAIT_CHANGE 0x0F
#define IMX_SIP_DDR_DVFS_GET_FREQ_COUNT 0x10
#define IMX_SIP_DDR_DVFS_GET_FREQ_INFO 0x11
#define FSL_SIP_SRC 0xc2000005
#define FSL_SIP_SRC_M4_START 0x00
...
...
@@ -94,8 +97,8 @@ int imx_hab_handler(uint32_t smc_fid, u_register_t x1,
u_register_t
x2
,
u_register_t
x3
,
u_register_t
x4
);
int
imx_noc_handler
(
uint32_t
smc_fid
,
u_register_t
x1
,
u_register_t
x2
,
u_register_t
x3
);
int
dram_dvfs_handler
(
uint32_t
smc_fid
,
u_register_t
x1
,
u_register_t
x2
,
u_register_t
x3
);
int
dram_dvfs_handler
(
uint32_t
smc_fid
,
void
*
handle
,
u_register_t
x1
,
u_register_t
x2
,
u_register_t
x3
);
#endif
uint64_t
imx_buildinfo_handler
(
uint32_t
smc_fid
,
u_register_t
x1
,
...
...
plat/imx/common/plat_imx8_gic.c
View file @
92c2de12
...
...
@@ -16,9 +16,7 @@
uintptr_t
rdistif_base_addrs
[
PLATFORM_CORE_COUNT
];
static
const
interrupt_prop_t
g01s_interrupt_props
[]
=
{
INTR_PROP_DESC
(
6
,
GIC_HIGHEST_SEC_PRIORITY
,
INTR_GROUP1S
,
GIC_INTR_CFG_LEVEL
),
INTR_PROP_DESC
(
7
,
GIC_HIGHEST_SEC_PRIORITY
,
INTR_PROP_DESC
(
8
,
GIC_HIGHEST_SEC_PRIORITY
,
INTR_GROUP0
,
GIC_INTR_CFG_LEVEL
),
};
...
...
plat/imx/imx8mm/gpc.c
View file @
92c2de12
...
...
@@ -587,6 +587,8 @@ static void imx8mm_tz380_init(void)
tzc380_configure_region
(
0
,
0x00000000
,
TZC_ATTR_REGION_SIZE
(
TZC_REGION_SIZE_4G
)
|
TZC_ATTR_REGION_EN_MASK
|
TZC_ATTR_SP_ALL
);
}
#define CCGR(x) (0x4000 + (x) * 16)
void
noc_wrapper_pre_suspend
(
unsigned
int
proc_num
)
{
uint32_t
val
;
...
...
@@ -603,9 +605,19 @@ void noc_wrapper_pre_suspend(unsigned int proc_num)
mmio_write_32
(
IMX_GPC_BASE
+
MST_CPU_MAPPING
,
val
);
/* noc can only be power down when all the pu domain is off */
if
(
!
pu_domain_status
)
if
(
!
pu_domain_status
)
{
/* enable noc power down */
imx_noc_slot_config
(
true
);
/*
* below clocks must be enabled to make sure RDC MRCs
* can be successfully reloaded.
*/
mmio_setbits_32
(
IMX_CCM_BASE
+
0xa300
,
(
0x1
<<
28
));
mmio_write_32
(
IMX_CCM_BASE
+
CCGR
(
5
),
0x3
);
mmio_write_32
(
IMX_CCM_BASE
+
CCGR
(
37
),
0x3
);
mmio_write_32
(
IMX_CCM_BASE
+
CCGR
(
87
),
0x3
);
}
}
/*
* gic redistributor context save must be called when
...
...
@@ -971,16 +983,16 @@ void imx_gpc_init(void)
/*
* Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x
1
;
* SW = 0x1, SW2ISO = 0x
8
;
* the CPU CORE and SCU power up timming counter
* is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768
*/
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
0
)
+
0x4
,
0x
8
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
1
)
+
0x4
,
0x
8
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
2
)
+
0x4
,
0x
8
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
3
)
+
0x4
,
0x
8
1
);
mmio_write_32
(
IMX_GPC_BASE
+
PLAT_PGC_PCR
+
0x4
,
0x
8
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
0
)
+
0x4
,
0x
40
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
1
)
+
0x4
,
0x
40
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
2
)
+
0x4
,
0x
40
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
3
)
+
0x4
,
0x
40
1
);
mmio_write_32
(
IMX_GPC_BASE
+
PLAT_PGC_PCR
+
0x4
,
0x
40
1
);
mmio_write_32
(
IMX_GPC_BASE
+
GPC_PGC_SCU_TIMMING
,
(
0x59
<<
10
)
|
0x5B
|
(
0x2
<<
20
));
...
...
plat/imx/imx8mn/gpc.c
View file @
92c2de12
...
...
@@ -459,7 +459,7 @@ void imx_set_rbc_count(void)
val
=
mmio_read_32
(
IMX_GPC_BASE
+
SLPCR
);
val
|=
SLPCR_RBC_EN
;
val
|=
(
0x
8
<<
SLPCR_RBC_SHIFT
);
val
|=
(
0x
a
<<
SLPCR_RBC_SHIFT
);
mmio_write_32
(
IMX_GPC_BASE
+
SLPCR
,
val
);
}
...
...
@@ -532,7 +532,6 @@ void imx_anamix_post_resume(void)
#define GPR_TZASC_EN (1 << 0)
#define GPR_TZASC_EN_LOCK (1 << 16)
#if 0
static
void
imx8mm_tz380_init
(
void
)
{
unsigned
int
val
;
...
...
@@ -547,7 +546,8 @@ static void imx8mm_tz380_init(void)
tzc380_configure_region
(
0
,
0x00000000
,
TZC_ATTR_REGION_SIZE
(
TZC_REGION_SIZE_4G
)
|
TZC_ATTR_REGION_EN_MASK
|
TZC_ATTR_SP_ALL
);
}
#endif
#define CCGR(x) (0x4000 + (x) * 16)
void
noc_wrapper_pre_suspend
(
unsigned
int
proc_num
)
{
...
...
@@ -565,9 +565,17 @@ void noc_wrapper_pre_suspend(unsigned int proc_num)
mmio_write_32
(
IMX_GPC_BASE
+
MST_CPU_MAPPING
,
val
);
/* noc can only be power down when all the pu domain is off */
// if (!pu_domain_status)
if
(
!
pu_domain_status
)
{
/* enable noc power down */
// imx_noc_slot_config(true);
imx_noc_slot_config
(
true
);
/*
* below clocks must be enabled to make sure RDC MRCs
* can be successfully reloaded.
*/
mmio_setbits_32
(
IMX_CCM_BASE
+
0xa300
,
(
0x1
<<
28
));
mmio_write_32
(
IMX_CCM_BASE
+
CCGR
(
5
),
0x3
);
mmio_write_32
(
IMX_CCM_BASE
+
CCGR
(
87
),
0x3
);
}
}
/*
* gic redistributor context save must be called when
...
...
@@ -594,9 +602,9 @@ void noc_wrapper_post_resume(unsigned int proc_num)
/* noc can only be power down when all the pu domain is off */
if
(
!
pu_domain_status
)
{
/* re-init the tz380 if resume from noc power down */
//
imx8mm_tz380_init();
imx8mm_tz380_init
();
/* disable noc power down */
//
imx_noc_slot_config(false);
imx_noc_slot_config
(
false
);
}
}
/* restore gic context */
...
...
@@ -666,9 +674,11 @@ static void imx_gpc_pm_domain_enable(uint32_t domain_id, uint32_t on)
}
if
(
domain_id
==
DISPMIX
)
{
/* special setting for DISPMIX */
/* mmio_write_32(0x32e28000, 0x7f); */
mmio_write_32
(
0x32e28004
,
0x1fff
);
/* de-reset bus_blk clk and
* enable bus_blk clk
*/
mmio_write_32
(
0x32e28000
,
0x100
);
mmio_write_32
(
0x32e28004
,
0x100
);
}
/* handle the ADB400 sync */
...
...
@@ -683,8 +693,6 @@ static void imx_gpc_pm_domain_enable(uint32_t domain_id, uint32_t on)
;
}
}
else
{
return
;
pu_domain_status
&=
~
(
1
<<
domain_id
);
if
(
domain_id
==
OTG1
)
...
...
@@ -703,6 +711,11 @@ static void imx_gpc_pm_domain_enable(uint32_t domain_id, uint32_t on)
;
}
if
(
domain_id
==
DISPMIX
)
{
mmio_write_32
(
0x32e28000
,
0x0
);
mmio_write_32
(
0x32e28004
,
0x0
);
}
/* HSIOMIX has no PU bit, so skip for it */
if
(
domain_id
!=
HSIOMIX
)
{
/* set the PGC bit */
...
...
@@ -754,16 +767,16 @@ void imx_gpc_init(void)
/*
* Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x
1
;
* SW = 0x1, SW2ISO = 0x
8
;
* the CPU CORE and SCU power up timming counter
* is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768
*/
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
0
)
+
0x4
,
0x
8
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
1
)
+
0x4
,
0x
8
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
2
)
+
0x4
,
0x
8
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
3
)
+
0x4
,
0x
8
1
);
mmio_write_32
(
IMX_GPC_BASE
+
PLAT_PGC_PCR
+
0x4
,
0x
8
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
0
)
+
0x4
,
0x
40
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
1
)
+
0x4
,
0x
40
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
2
)
+
0x4
,
0x
40
1
);
mmio_write_32
(
IMX_GPC_BASE
+
COREx_PGC_PCR
(
3
)
+
0x4
,
0x
40
1
);
mmio_write_32
(
IMX_GPC_BASE
+
PLAT_PGC_PCR
+
0x4
,
0x
40
1
);
mmio_write_32
(
IMX_GPC_BASE
+
GPC_PGC_SCU_TIMMING
,
(
0x59
<<
10
)
|
0x5B
|
(
0x2
<<
20
));
...
...
@@ -789,10 +802,12 @@ void imx_gpc_init(void)
*/
mmio_clrbits_32
(
IMX_SRC_BASE
+
0x20
,
0x1
);
#if 0
/* enable all power domain by default for bringup purpose */
mmio_write_32(0x303844f0, 0x3);
mmio_write_32(0x30384570, 0x3);
mmio_write_32(IMX_GPC_BASE + 0xf8, (1 << 10) | (1 << 7) | (1 << 2) | (1 << 0));
#endif
}
int
imx_gpc_handler
(
uint32_t
smc_fid
,
...
...
plat/imx/imx8mn/imx8mn_bl31_setup.c
View file @
92c2de12
...
...
@@ -54,6 +54,8 @@ IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
#define SMC_CMD_ALLOC_PAGE 0x01
/* allocate page to this partition */
#define SMC_CMD_DEALLOC_PART 0x03
/* deallocate partition */
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
static
entry_point_info_t
bl32_image_ep_info
;
static
entry_point_info_t
bl33_image_ep_info
;
...
...
@@ -203,6 +205,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/* config the caam access permission */
imx8mn_caam_config
();
/*
* ROM enabled the RDC config for OCRAM space, just disable
* it. it can be reconfigured based on the system requirement.
*/
mmio_write_32
(
IMX_RDC_BASE
+
0x908
,
0xff
);
mmio_write_32
(
IMX_RDC_BASE
+
0x918
,
0xff
);
mmio_write_32
(
IMX_RDC_BASE
+
0x928
,
0xff
);
#if DEBUG_CONSOLE
console_uart_register
(
IMX_BOOT_UART_BASE
,
IMX_BOOT_UART_CLK_IN_HZ
,
IMX_CONSOLE_BAUDRATE
,
&
console
);
...
...
@@ -222,11 +232,20 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
SET_SECURITY_STATE
(
bl32_image_ep_info
.
h
.
attr
,
SECURE
);
bl32_image_ep_info
.
pc
=
BL32_BASE
;
bl32_image_ep_info
.
spsr
=
0
;
#ifdef SPD_trusty
bl32_image_ep_info
.
args
.
arg0
=
BL32_SIZE
;
bl32_image_ep_info
.
args
.
arg1
=
BL32_BASE
;
#endif
/* Pass TEE base and size to uboot */
bl33_image_ep_info
.
args
.
arg1
=
0xBE000000
;
bl33_image_ep_info
.
args
.
arg2
=
0x2000000
;
#endif
bl31_tzc380_setup
();
/* Assign M7 to domain 1 */
mmio_write_32
(
IMX_RDC_BASE
+
0x204
,
0x1
);
mmio_write_32
(
IMX_RDC_BASE
+
0x518
,
0xfc
);
mmio_write_32
(
IMX_RDC_BASE
+
0x5A4
,
0xf3
);
}
void
bl31_plat_arch_setup
(
void
)
...
...
@@ -252,6 +271,11 @@ void bl31_plat_arch_setup(void)
mmap_add_region
(
0x3c000000
,
0x3c000000
,
0x4000000
,
MT_DEVICE
|
MT_RW
);
mmap_add_region
(
OCRAM_S_BASE
,
OCRAM_S_BASE
,
OCRAM_S_SIZE
,
MT_MEMORY
|
MT_RW
);
#ifdef SPD_trusty
mmap_add_region
(
BL32_BASE
,
BL32_BASE
,
BL32_SIZE
,
MT_MEMORY
|
MT_RW
);
#endif
#if USE_COHERENT_MEM
mmap_add_region
(
BL31_COHERENT_RAM_BASE
,
BL31_COHERENT_RAM_BASE
,
BL31_COHERENT_RAM_LIMIT
-
BL31_COHERENT_RAM_BASE
,
...
...
@@ -305,3 +329,12 @@ void bl31_plat_runtime_setup(void)
{
return
;
}
#ifdef SPD_trusty
void
plat_trusty_set_boot_args
(
aapcs64_params_t
*
args
)
{
args
->
arg0
=
BL32_SIZE
;
args
->
arg1
=
BL32_BASE
;
args
->
arg2
=
TRUSTY_PARAMS_LEN_BYTES
;
}
#endif
plat/imx/imx8mn/imx8mn_psci.c
View file @
92c2de12
...
...
@@ -13,6 +13,7 @@
#include <psci.h>
#include <mmio.h>
#include <soc.h>
#include <delay_timer.h>
#define SNVS_LPCR 0x38
...
...
@@ -143,15 +144,16 @@ void imx_domain_suspend_finish(const psci_power_state_t *target_state)
/* clear the system wakeup setting */
imx_set_sys_wakeup
(
core_id
,
false
);
imx_anamix_post_resume
();
imx_clear_rbc_count
();
if
(
!
imx_is_m4_enabled
()
||
!
imx_m4_lpa_active
())
dram_exit_retention
();
noc_wrapper_post_resume
(
core_id
);
}
/* check the cluster level power status */
if
(
!
is_local_state_run
(
CLUSTER_PWR_STATE
(
target_state
)))
if
(
!
is_local_state_run
(
CLUSTER_PWR_STATE
(
target_state
)))
{
imx_clear_rbc_count
();
imx_set_cluster_powerdown
(
core_id
,
PSCI_LOCAL_STATE_RUN
);
}
/* check the core level power status */
if
(
is_local_state_off
(
CORE_PWR_STATE
(
target_state
)))
{
...
...
@@ -207,8 +209,17 @@ void __dead2 imx_system_off(void)
void
__dead2
imx_pwr_domain_pwr_down_wfi
(
const
psci_power_state_t
*
target_state
)
{
if
(
is_local_state_off
(
CLUSTER_PWR_STATE
(
target_state
)))
{
/*
* before enter WAIT or STOP mode with PLAT(SCU) power down,
* rbc count need to be enabled to make sure PLAT is
* power down successfully even if the the wakeup IRQ is pending
* early before the power down sequence. the RBC counter is
* drived by the 32K OSC, so delay 30us to make sure the counter
* is really running.
*/
if
(
!
is_local_state_run
(
CLUSTER_PWR_STATE
(
target_state
)))
{
imx_set_rbc_count
();
udelay
(
30
);
}
while
(
1
)
...
...
plat/imx/imx8mn/include/platform_def.h
View file @
92c2de12
...
...
@@ -27,6 +27,11 @@
#define BL31_LIMIT 0x980000
#define BL32_BASE 0xbe000000
#ifdef SPD_trusty
#define BL32_SIZE 0x02000000
#define BL32_LIMIT 0xC0000000
#endif
/* non-secure uboot base */
#define PLAT_NS_IMAGE_OFFSET 0x40200000
...
...
@@ -39,8 +44,13 @@
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
#ifdef SPD_trusty
#define MAX_XLAT_TABLES 5
#define MAX_MMAP_REGIONS 13
#else
#define MAX_XLAT_TABLES 4
#define MAX_MMAP_REGIONS 12
#endif
#define HAB_RVT_BASE 0x00000900
/* HAB_RVT for i.MX8MM */
...
...
plat/imx/imx8mq/imx8mq_bl31_setup.c
View file @
92c2de12
...
...
@@ -89,6 +89,7 @@ static struct rdc_mda_conf masters_config[] = {
#define AIY_MICRON_3G 0x1
#define AIY_MICRON_1G 0x5
#define AIY_HYNIX_1G 0x3
#define AIY_KINGSTON_2G 0x6
int
get_imx8m_baseboard_id
(
void
);
unsigned
long
tee_base_address
;
...
...
@@ -195,7 +196,10 @@ void bl31_tzc380_setup(void)
if
((
val
&
GPR_TZASC_EN
)
!=
GPR_TZASC_EN
)
return
;
#ifndef SPD_trusty
/* Remove below log for trusty to save some memory. */
NOTICE
(
"Configuring TZASC380
\n
"
);
#endif
tzc380_init
(
IMX_TZASC_BASE
);
...
...
@@ -226,6 +230,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
if
(
board_id
==
AIY_MICRON_1G
||
board_id
==
AIY_HYNIX_1G
)
{
tee_base_address
=
(
unsigned
long
)
0x7e000000
;
}
else
if
(
board_id
==
AIY_KINGSTON_2G
){
tee_base_address
=
(
unsigned
long
)
0xbe000000
;
}
else
{
tee_base_address
=
(
unsigned
long
)
0xfe000000
;
}
...
...
plat/imx/imx8qm/imx8qm_bl31_setup.c
View file @
92c2de12
...
...
@@ -450,6 +450,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
sc_pm_set_resource_power_mode
(
ipc_handle
,
SC_R_CAAM_JR2_OUT
,
SC_PM_PW_MODE_ON
);
sc_pm_set_resource_power_mode
(
ipc_handle
,
SC_R_CAAM_JR3
,
SC_PM_PW_MODE_ON
);
sc_pm_set_resource_power_mode
(
ipc_handle
,
SC_R_CAAM_JR3_OUT
,
SC_PM_PW_MODE_ON
);
sc_pm_set_resource_power_mode
(
ipc_handle
,
SC_R_MU_4A
,
SC_PM_PW_MODE_ON
);
#endif
bl33_image_ep_info
.
pc
=
PLAT_NS_IMAGE_OFFSET
;
...
...
plat/imx/imx8qm/include/sec_rsrc.h
View file @
92c2de12
...
...
@@ -25,6 +25,7 @@ sc_rsrc_t secure_rsrcs[] = {
SC_R_CAAM_JR2_OUT
,
SC_R_CAAM_JR3
,
SC_R_CAAM_JR3_OUT
,
SC_R_MU_4A
,
#endif
SC_R_IRQSTR_SCU2
};
...
...
@@ -32,7 +33,6 @@ sc_rsrc_t secure_rsrcs[] = {
/* resources that have register access for non-secure domain */
sc_rsrc_t
ns_access_allowed
[]
=
{
SC_R_GIC
,
SC_R_GIC_SMMU
,
SC_R_GPT_0
,
SC_R_CCI
};
plat/imx/imx8qx/imx8qx_bl31_setup.c
View file @
92c2de12
...
...
@@ -426,6 +426,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
sc_pm_set_resource_power_mode
(
ipc_handle
,
SC_R_CAAM_JR2_OUT
,
SC_PM_PW_MODE_ON
);
sc_pm_set_resource_power_mode
(
ipc_handle
,
SC_R_CAAM_JR3
,
SC_PM_PW_MODE_ON
);
sc_pm_set_resource_power_mode
(
ipc_handle
,
SC_R_CAAM_JR3_OUT
,
SC_PM_PW_MODE_ON
);
sc_pm_set_resource_power_mode
(
ipc_handle
,
SC_R_MU_4A
,
SC_PM_PW_MODE_ON
);
#endif
bl33_image_ep_info
.
pc
=
PLAT_NS_IMAGE_OFFSET
;
...
...
plat/imx/imx8qx/include/sec_rsrc.h
View file @
92c2de12
...
...
@@ -20,6 +20,7 @@ sc_rsrc_t secure_rsrcs[] = {
SC_R_CAAM_JR2_OUT
,
SC_R_CAAM_JR3
,
SC_R_CAAM_JR3_OUT
,
SC_R_MU_4A
,
#endif
SC_R_IRQSTR_SCU2
};
...
...
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