Commit b2dff826 authored by Jacky Bai's avatar Jacky Bai

plat: imx8mn: Update the cpu core power up timing

Updating the CPU CORE power up timing to make sure
the RDC reload is done before CPU start to run code
in OCRAM space.
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
parent c260c0ef
......@@ -757,16 +757,16 @@ void imx_gpc_init(void)
/*
* Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x1;
* SW = 0x1, SW2ISO = 0x8;
* the CPU CORE and SCU power up timming counter
* is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768
*/
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x81);
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x81);
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x81);
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x81);
mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81);
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401);
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401);
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401);
mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401);
mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401);
mmio_write_32(IMX_GPC_BASE + GPC_PGC_SCU_TIMMING,
(0x59 << 10) | 0x5B | (0x2 << 20));
......
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