1. 11 Nov, 2019 1 commit
  2. 15 Oct, 2019 2 commits
  3. 30 Sep, 2019 1 commit
  4. 04 Sep, 2019 3 commits
  5. 28 Aug, 2019 1 commit
    • Ye Li's avatar
      MLK-22488 imx8qm: Remove SC_R_GIC_SMMU from non-secure access list · 0a0edb20
      Ye Li authored
      SC_R_GIC_SMMU is a master resource, we can't set peripheral
      permission to this resource, otherwise the API will return below error
      on latest SCFW, because SCFW has added a resource type check.
      On old SCFW, the API does nothing to a master resource. So remove the
      resource from ns_access_allowed array.
      
      ERROR: sc_rm_set_peripheral_permissions: rsrc 14, ret 3
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      0a0edb20
  6. 05 Aug, 2019 1 commit
  7. 31 Jul, 2019 1 commit
  8. 22 Jul, 2019 3 commits
  9. 17 Jul, 2019 1 commit
  10. 16 Jul, 2019 4 commits
  11. 12 Jul, 2019 1 commit
  12. 08 Jul, 2019 1 commit
  13. 04 Jul, 2019 1 commit
    • Jacky Bai's avatar
      plat: imx8mn: correct the noc power down setting · 685e3e26
      Jacky Bai authored
      The NOC power down is skipped by mistake before, so fix it.
      Additionally, the OCRAM memory region protection is enabled
      by ROM, but does NOT disable it. it should be disabled by
      default. if there are requirments for RDC memory region
      protection for OCRAM space, we can reconfigure it and enable
      it again.
      Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
      685e3e26
  14. 27 Jun, 2019 2 commits
  15. 25 Jun, 2019 3 commits
  16. 19 Jun, 2019 1 commit
    • Ji Luo's avatar
      MA-14989-3 Add 2GB ddr support for AIY · 61bfded5
      Ji Luo authored
      Specify the tee addr to 0xbe00_0000 for 2GB ddr AIY board.
      Remove some logs for trusty to save some memory or build
      will fail because of very limited ocram size on imx8mq.
      
      Test: build and boot on AIY 2GB board.
      
      Change-Id: I06d93857188cdda4829ad1f452755559af3983fe
      Signed-off-by: default avatarJi Luo <ji.luo@nxp.com>
      61bfded5
  17. 14 Jun, 2019 1 commit
  18. 06 Jun, 2019 2 commits
  19. 31 May, 2019 2 commits
    • Abel Vesa's avatar
      plat: imx8mq: gpc: Fix the gpc_saved_imrs offset for pdn · 9951e98e
      Abel Vesa authored
      The offset of the gpc_saved_imrs was computed wrong.
      Now, the offset is consistent between saving and restoring.
      
      Fixes: 0df4c895 ("plat: imx8mq: gpc: Add array for cores IMR offset")
      Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
      Reviewed-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
      9951e98e
    • Abel Vesa's avatar
      MLK-21399 plat: imx8mq: gpc: Workaround for ERR11171 · 0e91ff59
      Abel Vesa authored
      This new workaround takes advantage of the per core IMR registers in GPC in
      order to unmask the IRQ0, still generated by the 12bit in IOMUX_GPR register
      (which now remains always set), so it can only wake up one core at the time.
      Also, this entire workaround has now been moved here in TF-A, allowing the
      kernel side to be minimal.
      
      Another advantage this workaround brings is the removal of the 50us delay
      (which was necessary before in gic_raise_softirq in kernel) by allowing the
      core that is waking up to mask his own IRQ0 in the suspend finish callback.
      
      One important change here is the way the cores are woken up in
      dram_dvfs_handler. Since the wake up mechanism has changed from asserting the
      12th bit in IOMUX_GPR and leaving the IMR1 1st bit on for each core to exactly
      the reverse, that is, leaving the IOMUX_GPR 12th bit always set and then
      masking/unmasking the IMR1 1st bit for each independent core, we need to use
      the imx_gpc_core_wake to wake up the cores.
      
      Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off) from kernel
      (gic_raise_softirq), since the new cpuidle workaround does not need it in order
      to clean the IOMUX_GPC 12bit. For now, the udelay seems to be still needed
      in order to delay the affinity info OFF for the dying core. This is something
      that needs further investigation.
      Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
      Reviewed-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
      0e91ff59
  20. 29 May, 2019 1 commit
  21. 28 May, 2019 1 commit
  22. 27 May, 2019 2 commits
  23. 22 May, 2019 1 commit
  24. 13 May, 2019 1 commit
  25. 19 Apr, 2019 1 commit
  26. 08 Apr, 2019 1 commit