Commit bb69b290 authored by Christian Schilmoeller's avatar Christian Schilmoeller
Browse files

Added additional XOR gate to the WWAN page. This makes it possible that the...

Added additional XOR gate to the WWAN page. This makes it possible that the polarity of the SIM_DETECT signal is configurable by one single O-Ohm-resistor.
This adds more flexibility concerning modem choice, as there are both polarities of this signal used by different modem manufacturers.
Added placeholder symbol for modem card (which holds now datasheet/bom information). The MPCIE socket has datasheet information, too.
Picked two electrolytic capacitors (220uF/10V) by Panasonic by distributor TME.
parent cb1fc3ac
......@@ -265,6 +265,28 @@ X ~ 3 600 0 300 L 50 50 1 2 O I
ENDDRAW
ENDDEF
#
# 74LVC1G86
#
DEF 74LVC1G86 U 0 30 Y Y 1 F N
F0 "U" 100 0 50 H V C CNN
F1 "74LVC1G86" 25 -75 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
X GND 3 -50 -200 0 U 40 40 0 0 W N
X VCC 5 -50 300 100 D 40 40 0 0 W
A -520 0 262 495 -495 0 1 0 N -350 199 -350 -198
A -471 -2 281 457 -451 0 1 0 N -275 199 -273 -200
A -2 126 326 -897 -225 0 1 0 N 0 -199 299 2
A 4 -120 320 906 221 0 1 0 N 2 200 300 0
P 2 0 1 0 -275 -200 0 -200 N
P 2 0 1 0 -275 200 0 200 N
X ~ 1 -600 100 320 R 50 50 1 1 I
X ~ 2 -600 -100 320 R 50 50 1 1 I
X ~ 4 600 0 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# 74LVC2G241
#
DEF 74LVC2G241 U 0 0 Y Y 1 F N
......
......@@ -56,6 +56,11 @@ K 3 input OR
F http://www.ti.com/lit/ds/symlink/sn74lvc1g332.pdf
$ENDCMP
#
$CMP 74LVC1G86
D Single Gate XOR 2 inputs
K TTL XOR2
$ENDCMP
#
$CMP 74LVC2G241
D IC BUFFER/DVR 3ST DL INV
$ENDCMP
......
......@@ -306,6 +306,28 @@ X ~ 3 600 0 300 L 50 50 1 2 O I
ENDDRAW
ENDDEF
#
# 74LVC1G86
#
DEF 74LVC1G86 U 0 30 Y Y 1 F N
F0 "U" 100 0 50 H V C CNN
F1 "74LVC1G86" 25 -75 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
X GND 3 -50 -200 0 U 40 40 0 0 W N
X VCC 5 -50 300 100 D 40 40 0 0 W
A -520 0 262 495 -495 0 1 0 N -350 199 -350 -198
A -471 -2 281 457 -451 0 1 0 N -275 199 -273 -200
A -2 126 326 -897 -225 0 1 0 N 0 -199 299 2
A 4 -120 320 906 221 0 1 0 N 2 200 300 0
P 2 0 1 0 -275 -200 0 -200 N
P 2 0 1 0 -275 200 0 200 N
X ~ 1 -600 100 320 R 50 50 1 1 I
X ~ 2 -600 -100 320 R 50 50 1 1 I
X ~ 4 600 0 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# 74LVC2G241
#
DEF 74LVC2G241 U 0 0 Y Y 1 F N
......@@ -2687,19 +2709,19 @@ ENDDEF
# ModemCard
#
DEF ModemCard MOD 0 40 Y Y 1 F N
F0 "MOD" 0 350 60 H V C CNN
F1 "ModemCard" 0 250 60 H V C CNN
F2 "" 0 -50 60 H I C CNN
F3 "" 0 -50 60 H I C CNN
F0 "MOD" -175 400 60 H V C CNN
F1 "ModemCard" -175 275 60 H V C CNN
F2 "" 575 250 60 H I C CNN
F3 "" 575 250 60 H I C CNN
DRAW
A -600 0 50 -899 899 0 0 0 N -600 -50 -600 50
T 0 0 150 60 0 0 0 3G/4G~Mobile Normal 0 C C
T 0 50 50 60 0 0 0 Communications~Adapter Normal 0 C C
T 0 0 -150 60 0 0 0 "Key ID ''B''" Normal 0 C C
T 0 50 -350 60 0 0 0 length:~42~mm Normal 0 C C
T 0 0 -50 60 0 0 0 M.2~Form~Factor Normal 0 C C
T 0 50 -250 60 0 0 0 width:~30~mm Normal 0 C C
P 10 0 0 0 -600 50 -600 450 600 450 600 350 700 350 700 -350 600 -350 600 -450 -600 -450 -600 -50 f
A 575 200 25 901 -901 0 0 0 N 575 225 575 175
T 0 -150 100 60 0 0 0 2G/3G/4G~Mobile Normal 0 C C
T 0 -175 0 60 0 0 0 Communications~Adapter Normal 0 C C
T 0 -200 -350 60 0 0 0 full~size Normal 0 C C
T 0 -150 -250 60 0 0 0 Mini~PCIE~form~factor Normal 0 C C
P 4 0 0 0 575 -450 725 -450 725 175 575 175 N
P 4 0 0 0 575 225 725 225 725 450 575 450 N
P 7 0 0 0 575 450 575 575 -700 575 -925 575 -925 -575 575 -575 575 -450 f
ENDDRAW
ENDDEF
#
......
(module 74LVC1G86 (layer F.Cu) (tedit 5B2BC6C6)
(descr https://www.nxp.com/docs/en/package-information/SOT753.pdf)
(tags 74LVC1G08)
(solder_mask_margin 0.05)
(solder_paste_margin -0.05)
(attr smd)
(fp_text reference REF** (at 0 -2.9) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LVC1G86 (at 0 2.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.075)))
)
(fp_line (start -0.9 1.61) (end 0.9 1.61) (layer F.SilkS) (width 0.12))
(fp_line (start 0.9 -1.61) (end -1.55 -1.61) (layer F.SilkS) (width 0.12))
(fp_line (start -1.9 -1.8) (end 1.9 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.9 -1.8) (end 1.9 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.9 1.8) (end -1.9 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.9 1.8) (end -1.9 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.9 -0.9) (end -0.25 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 -1.55) (end -0.25 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start -0.9 -0.9) (end -0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 1.55) (end -0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 -1.55) (end 0.9 1.55) (layer F.Fab) (width 0.1))
(pad 1 smd rect (at -1.2 -0.95) (size 0.8 0.55) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -1.2 0) (size 0.8 0.55) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at -1.2 0.95) (size 0.8 0.55) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at 1.2 0.95) (size 0.8 0.55) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at 1.2 -0.95) (size 0.8 0.55) (layers F.Cu F.Paste F.Mask))
(model ${KISYS3DMOD}/TO_SOT_Packages_SMD.3dshapes/SOT-23-5.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module mpcie-outline (layer F.Cu) (tedit 541E5E95)
(fp_text reference Ref** (at 12.15 -15.2 90) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value Val** (at 14.1 -15.25 90) (layer F.SilkS) hide
(effects (font (thickness 0.15)))
)
(fp_line (start 15 -48.05) (end -15 -48.05) (layer F.SilkS) (width 0.01))
(fp_text user "IO Connector Region" (at 0.55 -45.65) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 15 -42.95) (end -15 -42.95) (layer F.SilkS) (width 0.01))
(fp_text user Center (at -0.15 -40.75 90) (layer F.SilkS)
(effects (font (size 0.25 0.25) (thickness 0.025)))
)
(fp_line (start -15 -5.1) (end 15 -5.1) (layer B.SilkS) (width 0.01))
(fp_line (start -3 -4.15) (end -3 -3.2) (layer F.SilkS) (width 0.01))
(fp_line (start -3 -3.2) (end 15 -3.2) (layer F.SilkS) (width 0.01))
(fp_line (start -4.5 -3.2) (end -4.5 -4.2) (layer F.SilkS) (width 0.01))
(fp_line (start -4.5 -4.2) (end -3 -4.2) (layer F.SilkS) (width 0.01))
(fp_line (start 15 -3.2) (end 13.65 -3.2) (layer Eco2.User) (width 0.01))
(fp_arc (start 13.65 -2.4) (end 12.85 -2.4) (angle 90) (layer B.CrtYd) (width 0.01))
(fp_line (start -13.65 -3.2) (end -15 -3.2) (layer B.CrtYd) (width 0.01))
(fp_arc (start -13.65 -2.4) (end -13.65 -3.2) (angle 90) (layer B.CrtYd) (width 0.01))
(fp_line (start -12.85 0) (end -12.85 -2.4) (layer B.CrtYd) (width 0.01))
(fp_line (start 12.85 0) (end 12.85 -2.4) (layer B.CrtYd) (width 0.01))
(fp_line (start -15 -3.2) (end -4.5 -3.2) (layer F.SilkS) (width 0.01))
(fp_text user Center (at -0.2 -14.35 90) (layer F.SilkS)
(effects (font (size 0.25 0.25) (thickness 0.025)))
)
(fp_line (start -3 0) (end 12.85 0) (layer B.CrtYd) (width 0.01))
(fp_line (start -15 -50.95) (end -15 -3.2) (layer B.CrtYd) (width 0.01))
(fp_line (start 15 -50.95) (end -15 -50.95) (layer B.CrtYd) (width 0.01))
(fp_line (start 15 -3.2) (end 15 -50.95) (layer B.CrtYd) (width 0.01))
(fp_line (start 0 0) (end 0 -50.95) (layer Eco1.User) (width 0.01))
(fp_line (start -3.75 -4.5) (end -3.75 -0.15) (layer Eco1.User) (width 0.01))
(fp_arc (start -3.75 -3.25) (end -4.5 -3.25) (angle 180) (layer F.Fab) (width 0.01))
(fp_line (start -4.5 0) (end -4.5 -3.25) (layer B.CrtYd) (width 0.01))
(fp_line (start -3 0) (end -3 -3.25) (layer B.CrtYd) (width 0.01))
(fp_line (start -4.5 0) (end -12.85 0) (layer B.CrtYd) (width 0.01))
(pad "" connect rect (at 12.1 -23.9) (size 5.8 5.8) (layers B.SilkS))
(pad "" np_thru_hole circle (at -12.1 -48.05) (size 2.6 2.6) (drill 2.6) (layers *.Cu *.Mask F.SilkS))
(pad "" connect rect (at 12.1 -9) (size 5.8 5.8) (layers B.SilkS))
(pad "" connect rect (at -12.1 -9) (size 5.8 5.8) (layers B.SilkS))
(pad "" connect rect (at -12.1 -23.9) (size 5.8 5.8) (layers B.SilkS))
(pad "" np_thru_hole circle (at 12.1 -48.05) (size 2.6 2.6) (drill 2.6) (layers *.Cu *.Mask F.SilkS))
(pad "" connect rect (at -12.1 -48.05) (size 5.8 5.8) (layers B.SilkS))
(pad "" connect rect (at 12.1 -48.05) (size 5.8 5.8) (layers B.SilkS))
(pad "" connect rect (at -12.1 -33.35) (size 5.8 5.8) (layers B.SilkS))
(pad "" connect rect (at 12.1 -33.35) (size 5.8 5.8) (layers B.SilkS))
)
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