Commit c4d560e2 authored by Eric Kuzmenko's avatar Eric Kuzmenko
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Move the two tantalum capacitors which were on the "back" to the "front" side,...

Move the two tantalum capacitors which were on the "back" to the "front" side, make corrections to the battery holder footprint including a hole which was missing for plastic pillar dealy (3D model contradicts the recommended footprint, may need to be adjusted depending on prototypes), place the 3V3_P and 1V8_P bypass caps throughout the board (as well as two of the 5V_P caps)

Only 8 more 5V_P bypass caps need to be placed and the unrouted count will be 0!
parent a7ce31a2
This diff is collapsed.
(module BH18650 (layer F.Cu) (tedit 5B64BAC3)
(module BH18650 (layer F.Cu) (tedit 5B723118)
(fp_text reference REF** (at 0 -11.25) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
......@@ -27,13 +27,15 @@
(fp_line (start 37.65 -10.55) (end -37.65 -10.55) (layer F.SilkS) (width 0.15))
(fp_line (start 37.65 10.55) (end 37.65 -10.55) (layer F.Fab) (width 0.15))
(fp_line (start -37.65 10.55) (end 37.65 10.55) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole oval (at -35.75 0) (size 3 5) (drill 1.5) (layers *.Cu *.Mask)
(pad 2 thru_hole oval (at -35.7 0) (size 3 5) (drill 1.8) (layers *.Cu *.Mask)
(clearance 0.254) (thermal_width 0.9))
(pad 1 thru_hole oval (at 35.75 0) (size 3 5) (drill 1.5) (layers *.Cu *.Mask)
(pad 1 thru_hole oval (at 35.7 0) (size 3 5) (drill 1.8) (layers *.Cu *.Mask)
(clearance 0.254))
(pad "" np_thru_hole circle (at 27 0) (size 3 3) (drill 3) (layers *.Cu *.Mask)
(pad "" np_thru_hole circle (at 26.85 0) (size 3 3) (drill 3) (layers *.Cu *.Mask)
(solder_mask_margin 0.000001) (clearance 0.225))
(pad "" np_thru_hole circle (at -27 0) (size 3 3) (drill 3) (layers *.Cu *.Mask)
(pad "" np_thru_hole circle (at -26.85 0) (size 3 3) (drill 3) (layers *.Cu *.Mask)
(solder_mask_margin 0.000001) (clearance 0.225))
(pad "" np_thru_hole circle (at 34.25 9.7) (size 1.8 1.8) (drill 1.8) (layers *.Cu *.Mask)
(solder_mask_margin 0.000001) (clearance 0.225))
(model ${KIPRJMOD}/packages3d/BHC-18650-1P.wrl
(offset (xyz 43.02759935379028 15.51177976703644 0))
......
(module Speaker_flat_15x11x4mm (layer F.Cu) (tedit 5B615A96)
(module Speaker_flat_15x11x4mm (layer F.Cu) (tedit 5B723620)
(fp_text reference REF** (at 0 -6.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
......@@ -11,14 +11,14 @@
(fp_line (start -7.625 5.05) (end 5.6 5.05) (layer Edge.Cuts) (width 0.15))
(fp_line (start 7.025 3.625) (end 7.025 -3.625) (layer Edge.Cuts) (width 0.15))
(fp_line (start -7.625 -5.05) (end 5.6 -5.05) (layer Edge.Cuts) (width 0.15))
(fp_line (start -7.5 -5.5) (end -7.5 5.5) (layer F.SilkS) (width 0.15))
(fp_line (start -7.7 -5.5) (end -7.7 5.5) (layer F.SilkS) (width 0.15))
(fp_line (start 7.5 -5.5) (end 7.5 5.5) (layer F.SilkS) (width 0.15))
(fp_line (start 7.5 5.5) (end -7.5 5.5) (layer F.SilkS) (width 0.15))
(fp_line (start -7.5 -5.5) (end 7.5 -5.5) (layer F.SilkS) (width 0.15))
(fp_line (start 7.5 5.5) (end -7.7 5.5) (layer F.SilkS) (width 0.15))
(fp_line (start -7.7 -5.5) (end 7.5 -5.5) (layer F.SilkS) (width 0.15))
(fp_line (start 7.5 -5.5) (end 7.5 5.5) (layer F.Fab) (width 0.15))
(fp_line (start 6.5 5.5) (end -7.5 5.5) (layer F.Fab) (width 0.15))
(fp_line (start -7.5 5.5) (end -7.5 -5.5) (layer F.Fab) (width 0.15))
(fp_line (start -7.5 -5.5) (end 6.5 -5.5) (layer F.Fab) (width 0.15))
(fp_line (start 6.5 5.5) (end -7.7 5.5) (layer F.Fab) (width 0.15))
(fp_line (start -7.7 5.5) (end -7.7 -5.5) (layer F.Fab) (width 0.15))
(fp_line (start -7.7 -5.5) (end 6.5 -5.5) (layer F.Fab) (width 0.15))
(fp_line (start -7.8 -5.8) (end 7.8 -5.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 7.8 -5.8) (end 7.8 5.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 7.8 5.8) (end -7.8 5.8) (layer F.CrtYd) (width 0.15))
......
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