Commit dc0574de authored by Christian Schilmoeller's avatar Christian Schilmoeller
Browse files

Changed shape of pcb area to rounded corners.

parent b270ca43
......@@ -5,7 +5,7 @@
(no_connects 0)
(area 59.924999 49.924999 150.075001 230.075001)
(thickness 1.6)
(drawings 4)
(drawings 8)
(tracks 0)
(zones 0)
(modules 0)
......@@ -108,9 +108,13 @@
(uvia_drill 0.1)
)
(gr_line (start 60 50) (end 60 230) (layer Edge.Cuts) (width 0.15))
(gr_line (start 150 50) (end 60 50) (layer Edge.Cuts) (width 0.15))
(gr_line (start 150 230) (end 150 50) (layer Edge.Cuts) (width 0.15))
(gr_line (start 60 230) (end 150 230) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 135 65) (end 135 50) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 75 65) (end 60 65) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 135 215) (end 150 215) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_arc (start 75 215) (end 75 230) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 60 65) (end 60 215) (layer Edge.Cuts) (width 0.15))
(gr_line (start 135 50) (end 75 50) (layer Edge.Cuts) (width 0.15))
(gr_line (start 150 215) (end 150 65) (layer Edge.Cuts) (width 0.15))
(gr_line (start 75 230) (end 135 230) (layer Edge.Cuts) (width 0.15))
)
(kicad_pcb (version 4) (host pcbnew 4.0.7+dfsg1-1)
(general
(links 0)
(no_connects 0)
(area 59.924999 59.924999 150.075001 230.075001)
(thickness 1.6)
(drawings 4)
(tracks 0)
(zones 0)
(modules 0)
(nets 1)
)
(page A4 portrait)
(title_block
(title "Librem 5 Dev Kit")
(date 2018-06-18)
(rev v0.1.0)
(company "Copyright 2018 GNU GPLv3")
(comment 1 eric.kuzmenko@puri.sm)
(comment 2 angus.ainslie@puri.sm)
(comment 3 nicole.faerber@puri.sm)
(comment 4 christian.schilmoeller@puri.sm)
)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x00030_80000001)
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net_class Default "Dies ist die voreingestellte Netzklasse."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
)
(gr_line (start 60 50) (end 60 230) (layer Edge.Cuts) (width 0.15))
(gr_line (start 150 50) (end 60 50) (layer Edge.Cuts) (width 0.15))
(gr_line (start 150 230) (end 150 50) (layer Edge.Cuts) (width 0.15))
(gr_line (start 60 230) (end 150 230) (layer Edge.Cuts) (width 0.15))
)
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment