Flip the direction of FULL_CARD_POWER_OFF# and W_DISABLE*# switches such that the devices are on when the switch is open, this should ever so slightly reduce the power consumption when these devices are used (most likely more often than them being off)

Connect the USB/SDIO bridge to WLAN rather than the uSD, fix a few ERC violations (not has zero errors/warnings), use best schottky option

deleted old USB hub and SDIO demultiplexer

fixed errors/typos in USB4640 part

Add current sense resistors and jumper symbols in the schematic, assign the various signals left unspecified, complete the PWR_EN assignment and verify that thepower sequence would be brought up in the correct order, add an LED to the VBAT_REG rail for debugging purposes (know when the board is receiving power)

Both the GP_LED1 and the HAPTIC motor are able to be controlled via PWM2 by individually MUXing the corresponding pads to PWM2. Only one pin should be MUXed to PWM2 at a time whilst the other is a GPIO, otherwise they will behave identically.

The I2C buses do not need the bus switch found on the EmCraft baseboard since the M.2 modules' power is controlled by PWR_EN and their I2C is level shifted between 1.8V<->3.3V, making it safe to leave them as is.

The various sense resistors have their corresponding parts selected but will be "NC" in the BoM and will not be assembled during manufacturing. To measure the current on the various rails (and WLAN M.2), one will need to break the trace between the two pads and place the corresponding resistor. A jumper (1.27 or 2.45 still needs to be determined) can be used to re-short these pads.

Notes have been added regarding which GPIO pins can easily be interchanged if it improves the layout.

Selected a better/cheaper RJ45 receptacle. Also picked out a well-suited green LED to be used in various spots throughout the board.

Include power load switch ICs to the 3.3V and 5V rails so that the SoC can disable the peripherals' power using the PWR_EN signal

Need to verify that 3V3's capacitance is greater than 3V3_P!

Next step is to have PWR_EN control the various logic translator chips EN pins.

Use a DP3T switch to select between eMMC, USB (serial download), and uSD boot devices, corrected the SW_BACK and SW_HOME buttons to have 33Ohm pull-ups instead
of pull-downs since the respective boot config lines have pull-downs already set

These buttons should be untouched during boot otherwise the board will not boot properly (pressing SW_HOME during boot causes "SD power cycle enable/eMMC reset enable" and pressing SW_BACK causes the uSD to be treated as a 4-bit bus if it's the boot device otherwise it's a BOOTCONFIG[6:4]=011 "reserved" condition)

Assign SAI5 to the WLAN/BT M.2, remove SIM2 slot due to conflicts between modules (specifically the L830-EB being a Config_0 module where the TX_BLANKING signal would connected to USIM_PWR2 sink), reassign the corresponding M.2 config pin to handle HP_DET, remove the AMOLED buck-boost as a different regulator will be used

The MIC_SEL, PROX_~INT, IMU_INT, and HAPTIC signals still need assigning

AND

Since pin 54 is actually USB_VBUS sink on the RedPine module the baseboard may need to treat this pin specially (NXP EVK uses a NMOS inverter with a 10k pull-up to 3V3).

Using a PFET to switch the high-side. The motor will likely be coin-shaped with adhesive on the back to stick to a designated spot on the board and have a 2-pin Molex or JST connector installed on the wire leads (by request).

Add NOR flash chip schematic, use mini-HDMI (requested) instead of micro and add its corresponding properties and footprint, use 3.5mm CTIA headset jack with through-hole pins rather than an SMD one for extra "mechanical rigidity"

Will likely want to use a USB-C receptacle with through-hole shield pins.

Add +X direction in the IMU's footprint on the F.SilkS layer, include figures in the schematic which show the corresponding axis directions (for both gyro/accel & compass) with respect to the package's pin 1 indicator/indent

Also double checked the footprint's pad sizes against the given package dimensions (no landing pattern given).

Add Proximity+Ambient Light sensor and 9-axis IMU circuits to the "sensors" schematic sheet, include the associated footprints and assign them to the respective symbols

The 9-axis IMU is configured to use I2C(1) rather than SPI. Notes are included regarding the IMU's setup. Descriptions of the IMU state that it is "fully compliant with Android" and therefore drivers must be available.

og SPDT switch to select internal or external mic via software (GPIO), select sp
ecific 8Ohm SMD speaker and SMD -37dB passive 2 terminal microphone (2.2kOhm output impedance)

Also fix a small typo in the notes from the last commit.

Introduce a method to switch between built-in and headset microphone depending on the presence of something plugged into the 3.5mm headphone jack, included notes regarding measurements, simulations, and various findings for the headset/built-in mic opperation

Zener diode included to protect the GPIO pin against under/over voltage from HP_OUT. Schmitt-trigger inverted at the enable pin of the analog switch for some debouncing.

Continue with the audio CODEC schematic, selected a potential STIA 3.5mm headphone jack, use logic level shifters on the WWAN/BT M.2's UART and PCM interfaces since the M.2 spec states that these are 1.8V logic levels

Still need to assign the corresponding SAI interface for the BT.

Assign verious signals such as W_DISABLE1, W_DISABLE2, WWAN_DISABLE; reorder the hierarchy to make more sense; add "solid" graphic lines around the power signals on the top sheet for clarity

Organize the USB-C, Battery, and Power sheets at the top-level such that the power-flow makes more sense when reading the schematic

Add I2C interface to WiFi/BT M.2, select an appropriate dual 2-input AND gate IC for the W_DISABLE logic and add the corresponding debounce/pull-down circuit to the HKS for W_DISABLE

Notes have been included regarding the I2C logic level voltage. If the USB interface is used then the input voltage needs to be 5.0V (not 3.3V); therefore the USB interface and hub may need to be removed!

Several signals are unused by the RS9116 WiFi/BT module, as noted in the schematic.

Add demultiplexer to uSDHC2 for the uSD and WiFi's SDIO interfaces, include the DEMUX's (TS3A27518E) 24QFN footprint

Bring back the *-cache.lib file as it is a very important in case someone opens the schematic and is missing any of the symbols used

added library symbol and footprint of minipcie socket for later use

* changes in library to make footprints usable (esp. numbering scheme of SOM9
* assigned footprints to schematic symbols

Begin WiFi+BT M.2 socket circuit, connect the associated USB bus from the hub circuit, determined that the i.MX8M's UART's default POR state is such that CTS is an output and RTS is an input and assigned the signals accordingly

Complete more of the USB hub circuit, connect one of the downstream ports to the WWAN M.2 module, remove the unused VBUS rail, add notes regarding the USB-C port having its corresponding ID pin pulled low

Begin USB 2.0 hub circuit for M.2 modules, remove supervisory/voltage monitor/watchdog circuit since the EmCraft SoM implements it

USB 2.0 hub circuit still needs to be completed.

Modify the boot config pins such that the eMMC is an 8-bit bus, depressing a momentary push button switch during boot causes SD boot, and relevant options

Use the main 18650 battery for the RTC (instead of a coin-cell), include information about which battery has been narrowed down to be the best option (NCR18650BD), remove 2K EEPROM used for the board ID (MAC address) since it won't be used

Have the charge controller IC handle the USB-C DRP PD switch mechanism, notes added on what procedure is required to operate as sink/source and how to swap between these roles

The mainline kernel's TCPM implementation needs to be used in conjunction with the charge controller IC's interface. For example, if the TCPC (PTN5110HQ CC controller) has the USB configured as a sink role then the TCPM (i.MX8M) would read out the CC_STATUS and POWER_STATUS registers of the CC controller IC to know this is the case, and then it (i.MX8M) would configure the charge controller IC accordingly (sink current from VBUS).

Both the CC controller and charge controller's open-drain output interrupt pins are tied together, which means if either of them pull the line low then the i.MX8M needs to check both of their fault registers to determine if a fault has occured on either chip. If the INT pin wasn't pulled low due to a fault then a status update event from either chip may have triggered it, which needs to be determined, as well as the corresponding action taken. These INT pins may need to be separated if the software side is too complex, so long as there's a spare interrupt pins available.

Fast swap is not supported, and is not a requirement.

Include li-ion charge controller PMIC which implements VBAT UVLO, VBAT OVP, input/output OVP & OCP; completely removed the old buck-boost in favor of this fully integrated chip

The BQ25896 may be able to handle the USB-C DRP PD switch all on its own (needs further investigation).