GitLab

Use CMC-2242PBL-A part number instead of CMR-2747PB-A on the BoM (as ordered and stated in the schematic)

Make pin 6 VDD for U1301 (single 2-input OR) and U1504 (single 2-input AND) instead of pin 5 (NC), swap pins 2 and 5 of U1803's (dual 2-input AND) schematic symbol (functionally insignificant, does not affect the layout)

The single 3-input OR gate had no issues.

Increment the version number to v0.1.2 and improve some parts of the routing, remove a pointless via found on Net-(D1701-Pad2) on a top layer track

Update the CPW feedlines according to the manufacturer's new stackup, re-export all of the manufacturing files accordingly (using new v0.1.1 version number)

Make some small adjustments/improvements to the CLKO1, CLKO2, ENET_WoL, ENET_~INT, ENET_~RST, and USB1_SS_SEL routing and trace widths

Reduce the trace width of CLKO1 and CLKO2 on the inner layers to 0.127mm in order to keep their impedance at 50Ohms throughout their length, do the same for SD2_~RST & WIFI_WAKE, remove a pointless stub found on CLKO1 near U1302, update the version number in the schematics to v0.1.1 and re-export the schematics' PDF

Increment the version number to v0.1.1 in order to prepare for any future changes, move the battery's current requirements on the silkscreen slightly to the left in order to make room for the thermistor's reference designator

- In case of a diode with diode symbol inside, the designator was moved outsided the component rectangle
- In case of text crossing the rectangle, the font size was reduced.
- 0402 components were not touched, the rectangle is sometimes crossing the first and last character of the text (still readable in most cases).

Bring back some of the copper zone pad connection settings specific to a per-footprint basis, remove the solderpaste from the pi-matching circuits

These settings were reset when all of the footprints were updated.

Correct the fabrication note 4 now stating "see supplementary pdf" instead of "detail A", add RoHS mark on F.Silk layer

Increase various power-rated trace widths to being equal to the pad sizes they connect, make improvements to various power pin traces

Update the 1.8V inductor's footprint such that its solder mask does not have pointed ends and is a more uniform shape

Run the smartcard's IO trace on the top layer, away from the CLK line, the clock being surrounded by RST and SC1_C4 (unused)

This file was created by exporting both the Cmts.User layer, as well as the NPTH&PTH drills into separate DXF files, then combining them in the footprint editor, finally, this new footprint made from both of these is imported into the layout and re-exported as a single DXF.

Update the BoM with all part numbers from the "purchasing" BoM in NextCloud, update all manufacturing-related files after the last few commits' changes (including new assembly & fabrication files as requested)