Add new built-in mic's frequency response curve to the schematic and re-simulate the HP_DET pin circuit with the protection diode's SPICE model included

Replace the CMC-6022-37T microphoen with the CMC-2242PBL-A THT one since the old one cannot be surface mounted/reflowed, add the microphone's 3D model

The microphone's pin position/order is agrees with the manufacturer's "measurement circuit" from the datasheet such that the right (facing the top of the mic) terminal/pin is its GND (-).

Update the schematic symbols and footprints after upgrading to KiCad 5.0.0, fix all ERC and DRC violations after the new update/upgrade

Since each of these ICs will be powered at the same time as the SoM regardless of the PWR_EN state, they should share the same I2C bus as the PMIC.

Emcraft is also going to change this cap to 2.2uF.

Now using GPIO5_IO03 (P4.03) to put the class-D op-amp in shutdown and conserve energy when muted, make C1716 near the ETH PHY's DVDDL pin 47 220nF instead of 10uF (EmCraft suggested that this should be 100nF but their's is 220nF, asked why), added a 10k pull-down to PAM2841's ENA pin, added a 100nF cap to the smart card's C1 VCC pin, added a 1uF cap to the haptic motor circuit's 3V3_P rail

Still need to use I2C3 instead of I2C1 according to EmCraft's suggestions.

Move the VBUS TVS diode and bypass caps and place copper pour on the respective pad areas, the VBUS rail has a 6mm wide fill zone in order to properly handle ~4.3A with a <10degreeC temperature rise (should also do this when bring VBUS to the charge controller), make the In4.Cu layer a solid ground layer

Move CAPTOUCH_~RST from BOOT_CFG_03 to GPIO1_IO05/P3.33 (was CSI_P2_PWDN), add a 10k pull-down to LCD_~RESET, make the corresponding changes to the BoM and netlist/layout

Having CAPTOUCH_~RST on BOOT_CFG_03 caused a voltage divider on the pin.

Route the PTC polyfuse that's on the VBUS rail using a copper pour on the In4.Cu layer, route the USB-C's shielding to parallel 0Ohm and NC cap to GND, add a power net class, add a 0.508mm annular ring 0.254mm drill via for power nets

Re-route the differential tracks going from the USB-C switch IC to the EMI&TVS ICs along with some of the passives around the USB-C switch chip (similar placement to EmCraft's), add a 1uF cap to the EN pin of the 2.8V LDO in order to introduce a small (~10ms) delay between the 1.8V rail coming up and the 2.8V rail

Rename all diff pairs such that they end in _P/_N rather than just P/N (underscore needed for diff pair routing)

Make the ETH PHY's crystal's load capacitors 27pF instead of 22pF, Cstray should now be 3.5pF instead of 7pF

Move USB-C, Mini-HDMI, RJ45, and 3.5mm jack receptacles to the bottom of the board, also place the Micro-SD card slot to the left of all of the receptacles centered at the bottom, place the Smart-Card slot just above the Micro-SD card facing the left, add 3D models to each of the respective connectors/sockets

The order of the various receptacles and sockets can be changed bit the pitch between them should stay about the same since it is currently as tightly packed asreasonably possible (1.5~2.5mm clearance between connectors).

Replace resistors which have specific values that can be converted to more common values in order to reduce the total number of unique BoM line items

Replace the VCNL4040 proximity+ambient light sensor's 470nF bypass cap on VDD with a 1uF one to reduce the number of BoM line items, also replace the USB Hub+SDIO bridge chip's SDCD cap between the P-MOSFET's gate and drain with an 18pF capacitor instead of a 10pF for the same reason (reduce number of BoM line items)

Make some minor fixes to various components' properties and update the BoM with the respective changes, sort the BoM based on reference designator and value

Replace SZMM5Z3V3T1G with MMSZ4688 zener diode which has a higher reverse working voltage to ensure that HP_DET is at a strong HIGH level when headphones/headset are inserted into the jack, replace its SOD-523 footprint with the corresponding SOD-123 footprint from the spec sheet's recommended land pattern

Replace camera's schottky+resistor level-shifter circuit with the more functional TXB0101 dedicated IC

Assign placeholder footprints to WWAN antennae (identical to GNSS ones for now), add haptic motor schematic symbol and split up the connector and motor footprints, now ready to generate netlist and import it into Pcbew without errors

Add proper WWAN reset circuit using a MMBT2222A NPN BJT along with a 100nF cap and a TVS diode, make needed adjustements to the WWAN's SIM card circuit (UIM-CLK and UIM-RESET caps are NC & added 4.7k series resistor to SIM_DETECT_O#), assign the MMBT2222A footprint to KiCad's official SOT-23 footprint (identical to the spec sheet's recommended land pattern)

If necessary, the NC cap pads on UIM-CLK and UIM-RESET can be tested with various values during the first prototype debugging phase.

Add pull-up resistor to nCS pin of the NOR flash chip, make electrolytic caps tantalums again due to a the price difference not being significant

Add mounting holes to the schematic and assign the associated M2 hole footprint, add fiducial marks to schematic and assign the associated 1mm diameter copper with 2mm diameter solder mask opening footprint, make various visual adjustments throughout the schematic

Replace WWAN M.2 circuit with one intended for mPCIe modules, include 74LVC1G08 single 2-input AND gate, create the AND gate's footprint and use the official SOT-23-5 3D model

The mini-SIM slot will need to be replaced with one that has an active-LOW detection pin. Will want to see if we can find cheap electrolytic to replace a few of the tantalum caps with (not all since we still need some low ESR, high capacitance, low profile, caps).