Add NOR flash chip schematic, use mini-HDMI (requested) instead of micro and add its corresponding properties and footprint, use 3.5mm CTIA headset jack with through-hole pins rather than an SMD one for extra "mechanical rigidity"

Will likely want to use a USB-C receptacle with through-hole shield pins.

Add +X direction in the IMU's footprint on the F.SilkS layer, include figures in the schematic which show the corresponding axis directions (for both gyro/accel & compass) with respect to the package's pin 1 indicator/indent

Also double checked the footprint's pad sizes against the given package dimensions (no landing pattern given).

Add Proximity+Ambient Light sensor and 9-axis IMU circuits to the "sensors" schematic sheet, include the associated footprints and assign them to the respective symbols

The 9-axis IMU is configured to use I2C(1) rather than SPI. Notes are included regarding the IMU's setup. Descriptions of the IMU state that it is "fully compliant with Android" and therefore drivers must be available.

og SPDT switch to select internal or external mic via software (GPIO), select sp
ecific 8Ohm SMD speaker and SMD -37dB passive 2 terminal microphone (2.2kOhm output impedance)

Also fix a small typo in the notes from the last commit.

Introduce a method to switch between built-in and headset microphone depending on the presence of something plugged into the 3.5mm headphone jack, included notes regarding measurements, simulations, and various findings for the headset/built-in mic opperation

Zener diode included to protect the GPIO pin against under/over voltage from HP_OUT. Schmitt-trigger inverted at the enable pin of the analog switch for some debouncing.

Continue with the audio CODEC schematic, selected a potential STIA 3.5mm headphone jack, use logic level shifters on the WWAN/BT M.2's UART and PCM interfaces since the M.2 spec states that these are 1.8V logic levels

Still need to assign the corresponding SAI interface for the BT.

Assign verious signals such as W_DISABLE1, W_DISABLE2, WWAN_DISABLE; reorder the hierarchy to make more sense; add "solid" graphic lines around the power signals on the top sheet for clarity

Organize the USB-C, Battery, and Power sheets at the top-level such that the power-flow makes more sense when reading the schematic

Add I2C interface to WiFi/BT M.2, select an appropriate dual 2-input AND gate IC for the W_DISABLE logic and add the corresponding debounce/pull-down circuit to the HKS for W_DISABLE

Notes have been included regarding the I2C logic level voltage. If the USB interface is used then the input voltage needs to be 5.0V (not 3.3V); therefore the USB interface and hub may need to be removed!

Several signals are unused by the RS9116 WiFi/BT module, as noted in the schematic.

Add demultiplexer to uSDHC2 for the uSD and WiFi's SDIO interfaces, include the DEMUX's (TS3A27518E) 24QFN footprint

Bring back the *-cache.lib file as it is a very important in case someone opens the schematic and is missing any of the symbols used

added library symbol and footprint of minipcie socket for later use

* changes in library to make footprints usable (esp. numbering scheme of SOM9
* assigned footprints to schematic symbols

Begin WiFi+BT M.2 socket circuit, connect the associated USB bus from the hub circuit, determined that the i.MX8M's UART's default POR state is such that CTS is an output and RTS is an input and assigned the signals accordingly

Complete more of the USB hub circuit, connect one of the downstream ports to the WWAN M.2 module, remove the unused VBUS rail, add notes regarding the USB-C port having its corresponding ID pin pulled low

Begin USB 2.0 hub circuit for M.2 modules, remove supervisory/voltage monitor/watchdog circuit since the EmCraft SoM implements it

USB 2.0 hub circuit still needs to be completed.

Modify the boot config pins such that the eMMC is an 8-bit bus, depressing a momentary push button switch during boot causes SD boot, and relevant options

Use the main 18650 battery for the RTC (instead of a coin-cell), include information about which battery has been narrowed down to be the best option (NCR18650BD), remove 2K EEPROM used for the board ID (MAC address) since it won't be used

Have the charge controller IC handle the USB-C DRP PD switch mechanism, notes added on what procedure is required to operate as sink/source and how to swap between these roles

The mainline kernel's TCPM implementation needs to be used in conjunction with the charge controller IC's interface. For example, if the TCPC (PTN5110HQ CC controller) has the USB configured as a sink role then the TCPM (i.MX8M) would read out the CC_STATUS and POWER_STATUS registers of the CC controller IC to know this is the case, and then it (i.MX8M) would configure the charge controller IC accordingly (sink current from VBUS).

Both the CC controller and charge controller's open-drain output interrupt pins are tied together, which means if either of them pull the line low then the i.MX8M needs to check both of their fault registers to determine if a fault has occured on either chip. If the INT pin wasn't pulled low due to a fault then a status update event from either chip may have triggered it, which needs to be determined, as well as the corresponding action taken. These INT pins may need to be separated if the software side is too complex, so long as there's a spare interrupt pins available.

Fast swap is not supported, and is not a requirement.

Include li-ion charge controller PMIC which implements VBAT UVLO, VBAT OVP, input/output OVP & OCP; completely removed the old buck-boost in favor of this fully integrated chip

The BQ25896 may be able to handle the USB-C DRP PD switch all on its own (needs further investigation).

In the case where VBAT can drop below 3.3V then it may be required to use a buck-boost in place of the existing buck converter for the 3.3V rail; may need some testing. Using the +5V rail as an input would also work but would introduce additional losses. According to several sources, when a 18650 Li-ion reaches 3.3V it is practically depleted anyway. When the feedback voltage drops below the internal reference voltage the buck converter will be in its "low dropout operation" with a duty cycle of 100%, so the output voltage should closely follow the input voltage.

Removed the reverse current protection circuit from the last commit due to the requirement changing to only 18650 battery and USB-C being possible power sources

Next thing to add is the charging circuit when the USB-C is in sink mode/role

Protecting VBAT from when board is sinking current via USB C. Protects against reverse polarity at the DC jack.

In EmCraft's instance VBUS should only be 5V when sinking current but they must protect against the condition when VBUS>12V and DC_IN=12V. This may need testing.

Use "Start to sheet number*100 and use first free number" designation, any new component added to the schematic will occupy the next available number in that sheet

For example: if sheet 2 has R201-R215 and we add a new resistor it will become R216.

The ERC is now at the same state as the DART SoM schematic. Need to compare various aspects of the current schematic against the EmCraft reference design. The main buck-boost will likely need to be switched to a 5V regulator, or be configured to output 5V.

A regulator will likely need to be added which will output some VBAT voltage level (3.5~4.2V) for the M.2 cards. The SIM7100 for example requires at least 3.4V!

Add logic level shifter for WWAN PCM interface, assign CONFIG_0 to GPIO3_IO20, use SAI6 for WWAN PCM since the baseband modem can be either master or slave (e.g. SIM7100 is always master)

Add notes regarding the WWAN M.2's USB interface. The Emcraft SoM has NAND_CE3_B available for the DISABLE pin. Still need to select which pin will be used for CONFIG_1.