The highest VIH(min) it will get to is ~3.0V, which is completely fine.

Add a TXB0101 logic level translator to the LCD_RESET# signal, the VIH(max) if the LCD's reset pin is 1.8V so the voltage needs to be translated from 3.3V logic down to 1.8V logic

The active TXB0101 level translator is used so that the pin can continue to be externally pulled low by a 10k resistor. The behavior of having this pin supplied with a logic level exceed its maximum rating is unpredictable (could be fine but could also act in unexpected ways). The TXB0101 is already used in the design as U1302, so now there will be 2x of these per board. This also requires two additional 0402 X5R 10V 100nF caps (already have 87 per board of CL05A104MP5NNNC / EmCraft PN: E-CAP-003-01, will now be 89 per board).

Specify in the schematic note that the OV5640 camera's 7-bit slave address is actually 0x3C (not 0x78 which is it's 8-bit write address with the LSB r/w bit set as 0)

The OV5640's datasheet mistakenly says 0x78 for the SCCB slave address (it's supposed to say 0x3C). In binary representation it's 0111 110x, with x as the r/w bit.

The WP pin needs to be brought to ground for the write protect to not be enabled by the chip.

Re-exported the gerber files (fabrication drawing will need to be reproduced too).

Make pin 6 VDD for U1301 (single 2-input OR) and U1504 (single 2-input AND) instead of pin 5 (NC), swap pins 2 and 5 of U1803's (dual 2-input AND) schematic symbol (functionally insignificant, does not affect the layout)

The single 3-input OR gate had no issues.

Increment the version number to v0.1.2 and improve some parts of the routing, remove a pointless via found on Net-(D1701-Pad2) on a top layer track

Reduce the trace width of CLKO1 and CLKO2 on the inner layers to 0.127mm in order to keep their impedance at 50Ohms throughout their length, do the same for SD2_~RST & WIFI_WAKE, remove a pointless stub found on CLKO1 near U1302, update the version number in the schematics to v0.1.1 and re-export the schematics' PDF

Update the BoM with all part numbers from the "purchasing" BoM in NextCloud, update all manufacturing-related files after the last few commits' changes (including new assembly & fabrication files as requested)

Make the backlight boost converter compensation capacitor (C459) 10nF instead of 100nF (was a typo), make the charge controller's PMID capacitor (C302) 10uF instead of 8.2uF since it is a more common value and is what is being used on the charge controller's eval board, select a 10uF 0603 X5R capacitor rated for 25V for both the PMID cap and the 10uF cap on VBUS, update the .ods BoM with tolerances & ratings for the caps and resistors which will be supplied by the PCBA house, export the component-placement-list file (dvk-mx8m-bsb-all.pos) which gives the coordinates of all components with respect to the top-left fiducial mark, re-export the gerbers for preliminary review (add silkscreen which states that this is preliminary instead of a version number), make a few minor improvements to the board's routing in various spots, update the IMU footprint so that its silkscreen which gives the axis directions is visible on the board, some footprints were updated to be defined as SMD footprints in order to show up on the component-placement list (strictly through-hole components are not listed)

The 0603 10uF 25V caps have been ordered and will be shipped to wherever the assembly is done. This commit contains the preliminary materials which will be reviewed (BoM, .pos file, and gerbers all zipped).

Move some of the reference designators on the silkscreen layers to more visible positions where possible, update the schematic, BoM, footprint, and layout to reflect the fact that the dual 2-input AND gate (U1803) is actually a 74AUP2G08* part (no longer *LVC*)

The rest of the silkscreen designators still need to be placed in more visible/unobstructed locations. The BoM still needs to have tolerance & rating values enter for all passive components that will be supplied by the PCBA house.

Make the ENET_* traces on the top layer 53mils in order to ensure they have a 50Ohm single-ended impedence, move one of the 5V_P bypass caps close to the SoM end of the USB2 diff pair, add meanders to the ENET_TXC, ENET_TX_CTL, ENET_RX_CTL in order to ensure these segments are matched to the long ENET_RXC segment (56.051mm, the rest of the RGMII signals are <10mm skew from this length and don't need adjusting, re-route the SIM card such that UIM-RESET is routed in between UIM-CLK and UIM-DATA as recommended by a BB manufacturer

Add a 5.29x27.14mm Purism logo to the "back" silkscreen of the board, seen on the bottom left edge when facing the display, remove the old schematic rescue files which are remnants from the Kicad 5.0.0 upgrade

Increase the 22.4V LED backlight boost converter's output capacitor to 4.7uF, coarsely route the 22V4_P rail to the display

Increase the footprint size of C461 to 0603 and increase the value of R418 to 33k in order to be able to use common 1uF 0603 capacitors rated for 35V

The worst-case OVP with R417 and R418 being rated at 1% is 34.96V which is still below the 35V rating. The output voltage is typically 22.4V which is well below the voltage rating. Therefore these capitors should never experience a voltage above what they are rated for.

Re-route the USB hub + SD controller chip's DP0/DM0 as a 90Ohm diff pair which feeds back to the IC's DM/DP pins (17<->31 & 18<->32), re-route the WWAN and WLAN diff pairs after they were shoved in a previous commit (reapplied the meanders as well)

Place and route the JTAG circuit, place and route the BOOT_MODE slide switch circuit, place and route the user-LED circuit, place and route the top-level sheet passive components (I2C2 pull-ups, 5V_SOM, 3V3_OUT, & ENET_2V5 bypass caps, PWR_EN pull-down, USB2_VBUS voltage divider for SoC's comparator, etc), route the microphone to the analog audio switch IC, update the schematic, BoM, and footprints to reflect the MHF4 coax cable change (including them being 5cm long)

Unrouted count is now 324. The power circuit and the display are what is now left to be placed on the board, a few nets currently on the board still need to be connected (~120). 3V3_SNVS and various other misc. power rails still need to be routed on the power plane (vias need to be placed near pads).

JTAG header footprint is accessible from the display side (not underneath the display). User-LED is in a location as-close-as-possible to the bottom center of the board (somewhat near the microphone).

Serpentine bends still need to be added to the CSI to match the intra-pair skew, still need to move the prox sensor to the top of the board!

The return path for the antenna may have to have a 6.8nH Murata LQG15HN inductor installed on it (cutting the ground trace shorting the pads). The BoM was updated with the new components and everything was reannotated and updated (page 2's caps were out of order).

Route USB2 to the hub chip's upstream port and re-order & route each of the downstream ports to their respective locations (smartcard, mPCIe, & M.2), place and route the HDMI fuse, schottky diodes, TVS diodes, capacitors, and pull-up resistors, route the rest of the HDMI's interface to the SoM (HPD & I2C), adjust the GNSS antenna's CPW width using the PCB manufacturer's recommendation from their calculations

The HDMI circuit should be complete now. The GNSS & WiFi+BT antennae should also be complete. The GNSS module's RX & TX lines need to be routed next.

Add ANT-LTE-CER-T as the baseband modem antenna into the schematic and BoM, update the layout accordingly

The diff pairs going to the NFETs are exactly matched to 0 with their phase/skew; 1V8P still needs to be brought to them.

Coarsely route HDMI diff pairs from the SoM to the CMF&ESD chips, place the microphone in a position that does not interfere with either the HDMI circuit or the RJ45

The HDMI diff pairs will need to try to have 30mil clearance between each other at every point possible, in tight spaces this is not possible, even spacing will need to be adjusted in the following commit.

Needed to create the HDMI_HEAC_P/N labels to route Utility&HPD as diff pairs. Made cap C1905 NC, which is in parallel with a 0Ohm resistor between the HDMI sheilding and GND.

Place and route the BOOT_CFG* signals, correct a signal labelling mistake causing SAI1_RXD0 (BOOT_CFG00) to be connected to SAI1_TXD0 (BOOT_CFG08)

BOOT_MODE* still needs to be placed & routed, need to find a good location for the SMD slide switches.

Add WiFi+BT antenna footprint, add pi matching circuit to the WiFi+BT antennas' feedlines, increment the capacitor part numbers on page 18 after adding the new (NC) feedline caps and make the respective changes to the reference designators in the BoM