Reduce the trace width of CLKO1 and CLKO2 on the inner layers to 0.127mm in order to keep their impedance at 50Ohms throughout their length, do the same for SD2_~RST & WIFI_WAKE, remove a pointless stub found on CLKO1 near U1302, update the version number in the schematics to v0.1.1 and re-export the schematics' PDF

Increment the version number to v0.1.1 in order to prepare for any future changes, move the battery's current requirements on the silkscreen slightly to the left in order to make room for the thermistor's reference designator

- In case of a diode with diode symbol inside, the designator was moved outsided the component rectangle
- In case of text crossing the rectangle, the font size was reduced.
- 0402 components were not touched, the rectangle is sometimes crossing the first and last character of the text (still readable in most cases).

Bring back some of the copper zone pad connection settings specific to a per-footprint basis, remove the solderpaste from the pi-matching circuits

These settings were reset when all of the footprints were updated.

Correct the fabrication note 4 now stating "see supplementary pdf" instead of "detail A", add RoHS mark on F.Silk layer

Increase various power-rated trace widths to being equal to the pad sizes they connect, make improvements to various power pin traces

Update the 1.8V inductor's footprint such that its solder mask does not have pointed ends and is a more uniform shape

Run the smartcard's IO trace on the top layer, away from the CLK line, the clock being surrounded by RST and SC1_C4 (unused)

This file was created by exporting both the Cmts.User layer, as well as the NPTH&PTH drills into separate DXF files, then combining them in the footprint editor, finally, this new footprint made from both of these is imported into the layout and re-exported as a single DXF.

Update the BoM with all part numbers from the "purchasing" BoM in NextCloud, update all manufacturing-related files after the last few commits' changes (including new assembly & fabrication files as requested)

Corrected library entry.
New placement and wiring for resistors near U402 in layout.

The signal CLK02 (clock supply for ethernet PHY) was surrounded with GND traces to form a shield against the static field (25 Mhz present).
The same was done now with sigbal CLK01 (clock supply for camera)
.

Bring back the current version number (v0.1.0) on the back silkscreen by replacing the word "Preliminary" with it

Make the backlight boost converter compensation capacitor (C459) 10nF instead of 100nF (was a typo), make the charge controller's PMID capacitor (C302) 10uF instead of 8.2uF since it is a more common value and is what is being used on the charge controller's eval board, select a 10uF 0603 X5R capacitor rated for 25V for both the PMID cap and the 10uF cap on VBUS, update the .ods BoM with tolerances & ratings for the caps and resistors which will be supplied by the PCBA house, export the component-placement-list file (dvk-mx8m-bsb-all.pos) which gives the coordinates of all components with respect to the top-left fiducial mark, re-export the gerbers for preliminary review (add silkscreen which states that this is preliminary instead of a version number), make a few minor improvements to the board's routing in various spots, update the IMU footprint so that its silkscreen which gives the axis directions is visible on the board, some footprints were updated to be defined as SMD footprints in order to show up on the component-placement list (strictly through-hole components are not listed)

The 0603 10uF 25V caps have been ordered and will be shipped to wherever the assembly is done. This commit contains the preliminary materials which will be reviewed (BoM, .pos file, and gerbers all zipped).

Make the rest of the silkscreen designators visible (some must be underneath the RJ45 and battery holder), add silkscreen which identifies the mPCIe and M.2 card slots

Currently placed under the mPCI card, but other locations possible.

Move device designators on silkscreen layer to reasonable places where they are readable and not covered by obstacles.
This was not possible on all areas of the F.Silk layer, because there exist four spots with a very high density of components:
-Audio circuit
-Ethernet circuit
-USB-C circuit
-Components below the SIM socket.

Move some of the reference designators on the silkscreen layers to more visible positions where possible, update the schematic, BoM, footprint, and layout to reflect the fact that the dual 2-input AND gate (U1803) is actually a 74AUP2G08* part (no longer *LVC*)

The rest of the silkscreen designators still need to be placed in more visible/unobstructed locations. The BoM still needs to have tolerance & rating values enter for all passive components that will be supplied by the PCBA house.