Correct the fabrication note 4 now stating "see supplementary pdf" instead of "detail A", add RoHS mark on F.Silk layer

Increase various power-rated trace widths to being equal to the pad sizes they connect, make improvements to various power pin traces

Update the 1.8V inductor's footprint such that its solder mask does not have pointed ends and is a more uniform shape

Run the smartcard's IO trace on the top layer, away from the CLK line, the clock being surrounded by RST and SC1_C4 (unused)

This file was created by exporting both the Cmts.User layer, as well as the NPTH&PTH drills into separate DXF files, then combining them in the footprint editor, finally, this new footprint made from both of these is imported into the layout and re-exported as a single DXF.

Update the BoM with all part numbers from the "purchasing" BoM in NextCloud, update all manufacturing-related files after the last few commits' changes (including new assembly & fabrication files as requested)

Corrected library entry.
New placement and wiring for resistors near U402 in layout.

The signal CLK02 (clock supply for ethernet PHY) was surrounded with GND traces to form a shield against the static field (25 Mhz present).
The same was done now with sigbal CLK01 (clock supply for camera)
.

Bring back the current version number (v0.1.0) on the back silkscreen by replacing the word "Preliminary" with it

Make the backlight boost converter compensation capacitor (C459) 10nF instead of 100nF (was a typo), make the charge controller's PMID capacitor (C302) 10uF instead of 8.2uF since it is a more common value and is what is being used on the charge controller's eval board, select a 10uF 0603 X5R capacitor rated for 25V for both the PMID cap and the 10uF cap on VBUS, update the .ods BoM with tolerances & ratings for the caps and resistors which will be supplied by the PCBA house, export the component-placement-list file (dvk-mx8m-bsb-all.pos) which gives the coordinates of all components with respect to the top-left fiducial mark, re-export the gerbers for preliminary review (add silkscreen which states that this is preliminary instead of a version number), make a few minor improvements to the board's routing in various spots, update the IMU footprint so that its silkscreen which gives the axis directions is visible on the board, some footprints were updated to be defined as SMD footprints in order to show up on the component-placement list (strictly through-hole components are not listed)

The 0603 10uF 25V caps have been ordered and will be shipped to wherever the assembly is done. This commit contains the preliminary materials which will be reviewed (BoM, .pos file, and gerbers all zipped).

Make the rest of the silkscreen designators visible (some must be underneath the RJ45 and battery holder), add silkscreen which identifies the mPCIe and M.2 card slots

Currently placed under the mPCI card, but other locations possible.

Move device designators on silkscreen layer to reasonable places where they are readable and not covered by obstacles.
This was not possible on all areas of the F.Silk layer, because there exist four spots with a very high density of components:
-Audio circuit
-Ethernet circuit
-USB-C circuit
-Components below the SIM socket.

Move some of the reference designators on the silkscreen layers to more visible positions where possible, update the schematic, BoM, footprint, and layout to reflect the fact that the dual 2-input AND gate (U1803) is actually a 74AUP2G08* part (no longer *LVC*)

The rest of the silkscreen designators still need to be placed in more visible/unobstructed locations. The BoM still needs to have tolerance & rating values enter for all passive components that will be supplied by the PCBA house.

Add user-facing universal icons/symbols which will help the users identify common buttons/receptacles/sockes

The gerbers will be re-exported frequenty from now until the final prototype files, after which point the revision will need to be incremented if further changes are made.

Make the ENET_* traces on the top layer 53mils in order to ensure they have a 50Ohm single-ended impedence, move one of the 5V_P bypass caps close to the SoM end of the USB2 diff pair, add meanders to the ENET_TXC, ENET_TX_CTL, ENET_RX_CTL in order to ensure these segments are matched to the long ENET_RXC segment (56.051mm, the rest of the RGMII signals are <10mm skew from this length and don't need adjusting, re-route the SIM card such that UIM-RESET is routed in between UIM-CLK and UIM-DATA as recommended by a BB manufacturer

Changed width of RGMII traces to 0.127 mm.
Removed unnecessary tiny segments/stubs.

Increasing distance between signals and creating meanders.

in order to be able to adjust trace lengths.

Add a 5.29x27.14mm Purism logo to the "back" silkscreen of the board, seen on the bottom left edge when facing the display, remove the old schematic rescue files which are remnants from the Kicad 5.0.0 upgrade

Re-route the USB hub+SD chip's crystal circuit making it more symmetric, extend the length of the ETH PHY's XTLI trace going to the crystal in order to more closely match its length to the XTLO trace

Place and route the remaining 5V_P bypass caps which are spread throughout various spots on the board, get the unrouted count down to 0

Now that the unrouted count is 0, it is time to clean up the entire layout; improving various routing such as separating the SIM card slot's CLK & data and making the USB hub+SD chip's crystal routing symnetric. After that, the BoM needs to be updated with the passive components' tolerances, capacitors' temperature &  voltage ratings, and list recommended PNs which are shared with EmCraft's baseboard.

Move the two tantalum capacitors which were on the "back" to the "front" side, make corrections to the battery holder footprint including a hole which was missing for plastic pillar dealy (3D model contradicts the recommended footprint, may need to be adjusted depending on prototypes), place the 3V3_P and 1V8_P bypass caps throughout the board (as well as two of the 5V_P caps)

Only 8 more 5V_P bypass caps need to be placed and the unrouted count will be 0!

Use 5V_P as the inner plane AC-GND reference for the USB2 and USB smartcard diff pairs, move the C1821 electroyltic cap from the back side near the edge to the front under the SoM where there is space available, make the 3V3_P copper pour occupy areas which allow the C1822 electrolytic cap to have a lower impedance connection to the regulator and M.2/mPCIe loads (as well as bringing 3V3_P closer to other loads), create a large In3.Cu keepout area on the top of the board where the antennae are

Movement of other power nets to avoid crossing.
Change of polygon shape to prevent that they break in pieces.

Unrouted nets count is 60 (only capacitors outside board area).
Proximity sensor could be moved to even better position.