Commit 1963434a authored by Eric Kuzmenko's avatar Eric Kuzmenko

Move more symbols, sheets, and pins around on the front sheet to make it even...

Move more symbols, sheets, and pins around on the front sheet to make it even clearer, bring back the old hierarchical structure (again), bring back each sheet's title, add large text "titles" to each sheet reflecting what they are for

Still need to double check everything on the first page.
parent 5a2467be
This diff is collapsed.
......@@ -37,8 +37,8 @@ EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 24 24
Title "Librem5 development kit"
Sheet 3 24
Title "Battery"
Date "2018-06-11"
Rev "v0.1.0"
Comp "Copyright 2018 GNU GPLv3"
......@@ -48,10 +48,10 @@ Comment3 "nicole.faerber@puri.sm"
Comment4 "christian.schilmoeller@puri.sm"
$EndDescr
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F 2 "" H 7100 4500 50 0001 C CNN
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......@@ -91,10 +91,10 @@ F 3 "" H 4250 2800 50 0001 C CNN
-1 0 0 -1
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......@@ -113,10 +113,10 @@ F 3 "" H 4450 2900 50 0001 C CNN
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$EndComp
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F 2 "" H 4450 3100 50 0001 C CNN
F 3 "" H 4450 3100 50 0001 C CNN
......@@ -163,10 +163,10 @@ F 3 "" H 5800 3350 50 0001 C CNN
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L GND #PWR050
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F 2 "" H 5800 3550 50 0001 C CNN
F 3 "" H 5800 3550 50 0001 C CNN
......@@ -185,10 +185,10 @@ F 3 "" H 4350 3450 50 0001 C CNN
0 -1 -1 0
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L GND #PWR051
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F 0 "#PWR051" H 4150 3250 50 0001 C CNN
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F 2 "" H 4150 3500 50 0001 C CNN
F 3 "" H 4150 3500 50 0001 C CNN
......@@ -207,10 +207,10 @@ F 3 "" H 7450 2800 50 0001 C CNN
1 0 0 -1
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L GND #PWR052
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F 0 "#PWR052" H 6450 2800 50 0001 C CNN
F 1 "GND" H 6450 2900 50 0000 C CNN
F 2 "" H 6450 3050 50 0001 C CNN
F 3 "" H 6450 3050 50 0001 C CNN
......@@ -285,10 +285,10 @@ F 9 "https://octopart.com/search?q=semitec%20103ht&start=0" H 6300 4600 60 0001
1 0 0 -1
$EndComp
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L GND #PWR053
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F 0 "#PWR053" H 6100 4650 50 0001 C CNN
F 1 "GND" H 6100 4750 50 0000 C CNN
F 2 "" H 6100 4900 50 0001 C CNN
F 3 "" H 6100 4900 50 0001 C CNN
......@@ -312,10 +312,10 @@ EN_SRC
Text HLabel 3400 4900 0 60 Input ~ 0
EN_SNK
$Comp
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L VBAT_REG #PWR054
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F 0 "#PWR054" H 3400 2800 50 0001 C CNN
F 1 "VBAT_REG" H 3400 3100 50 0000 C CNN
F 2 "" H 3400 2950 50 0001 C CNN
F 3 "" H 3400 2950 50 0001 C CNN
......@@ -362,10 +362,10 @@ F 9 "https://octopart.com/search?q=LTST-C190GKT&start=0" V 3000 3150 60 0001 C
0 -1 -1 0
$EndComp
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F 0 "#PWR0275" H 3000 2800 50 0001 C CNN
F 0 "#PWR055" H 3000 2800 50 0001 C CNN
F 1 "VBAT_REG" H 3000 3100 50 0000 C CNN
F 2 "" H 3000 2950 50 0001 C CNN
F 3 "" H 3000 2950 50 0001 C CNN
......@@ -373,10 +373,10 @@ F 3 "" H 3000 2950 50 0001 C CNN
1 0 0 -1
$EndComp
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L GND #PWR056
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F 1 "GND" H 7100 4450 50 0000 C CNN
F 2 "" H 7100 4600 50 0001 C CNN
F 3 "" H 7100 4600 50 0001 C CNN
......@@ -401,10 +401,10 @@ F 9 "https://www.digikey.com/products/en/filters/ferrite-beads-and-chips/841?FV=
0 1 1 0
$EndComp
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L GND #PWR057
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F 0 "#PWR057" H 7450 2800 50 0001 C CNN
F 1 "GND" H 7450 2900 50 0000 C CNN
F 2 "" H 7450 3050 50 0001 C CNN
F 3 "" H 7450 3050 50 0001 C CNN
......@@ -443,10 +443,10 @@ I(Lsat)=7A
Text Notes 7850 4150 0 60 ~ 0
reference design: http://www.ti.com/lit/ug/sluuba2b/sluuba2b.pdf
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F 1 "PWR_FLAG" H 7450 2700 50 0000 C CNN
F 2 "" H 7450 2550 50 0001 C CNN
F 3 "" H 7450 2550 50 0001 C CNN
......@@ -454,10 +454,10 @@ F 3 "" H 7450 2550 50 0001 C CNN
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F 1 "PWR_FLAG" H 6400 4000 50 0000 C CNN
F 2 "" H 6400 3850 50 0001 C CNN
F 3 "" H 6400 3850 50 0001 C CNN
......@@ -482,10 +482,10 @@ F 9 "https://octopart.com/search?q=BQ25896&start=0" H 5050 3600 60 0001 C CNN "
1 0 0 -1
$EndComp
$Comp
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L GND #PWR060
U 1 1 5AED22FA
P 3800 5150
F 0 "#PWR0280" H 3800 4900 50 0001 C CNN
F 0 "#PWR060" H 3800 4900 50 0001 C CNN
F 1 "GND" H 3800 5000 50 0000 C CNN
F 2 "" H 3800 5150 50 0001 C CNN
F 3 "" H 3800 5150 50 0001 C CNN
......@@ -497,10 +497,10 @@ Text Notes 1050 5000 0 60 ~ 0
Text Notes 3475 3175 0 60 ~ 0
Default LOW:\nadapter source
$Comp
L GND #PWR0281
L GND #PWR061
U 1 1 5AF3ADC2
P 3850 3350
F 0 "#PWR0281" H 3850 3100 50 0001 C CNN
F 0 "#PWR061" H 3850 3100 50 0001 C CNN
F 1 "GND" H 3850 3200 50 0000 C CNN
F 2 "" H 3850 3350 50 0001 C CNN
F 3 "" H 3850 3350 50 0001 C CNN
......@@ -508,10 +508,10 @@ F 3 "" H 3850 3350 50 0001 C CNN
1 0 0 -1
$EndComp
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L VBUS #PWR062
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F 0 "#PWR062" H 4250 2400 50 0001 C CNN
F 1 "VBUS" H 4250 2700 50 0000 C CNN
F 2 "" H 4250 2550 50 0001 C CNN
F 3 "" H 4250 2550 50 0001 C CNN
......@@ -527,10 +527,10 @@ Also, reading PTN5110HQ's CC_STATUS and POWER_STATUS\nregisters will tell TCPM (
Text Notes 6650 4900 0 60 ~ 0
VBAT(DPL)=2.15~~2.5V
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F 0 "#PWR0283" H 6700 3700 50 0001 C CNN
F 0 "#PWR063" H 6700 3700 50 0001 C CNN
F 1 "VBAT" H 6700 4000 50 0000 C CNN
F 2 "" H 6700 3850 50 0001 C CNN
F 3 "" H 6700 3850 50 0001 C CNN
......@@ -539,7 +539,7 @@ F 3 "" H 6700 3850 50 0001 C CNN
$EndComp
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Scale 1,000000
Scale 1.000000
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63 00 00 00 03 73 42 49 54 08 08 08 DB E1 4F E0 00 00 20 00 49 44 41 54 78 9C EC BD 7B 7C 54 D5
......@@ -1982,10 +1982,10 @@ VBAT_REG
Text Notes 5050 1800 0 236 ~ 47
Battery Charge Controller
$Comp
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L GND #PWR064
U 1 1 5B0600CE
P 8700 3050
F 0 "#PWR0284" H 8700 2800 50 0001 C CNN
F 0 "#PWR064" H 8700 2800 50 0001 C CNN
F 1 "GND" H 8700 2900 50 0000 C CNN
F 2 "" H 8700 3050 50 0001 C CNN
F 3 "" H 8700 3050 50 0001 C CNN
......@@ -2354,10 +2354,10 @@ F 9 "https://www.digikey.com/products/en/capacitors/ceramic-capacitors/60?k=&pke
1 0 0 -1
$EndComp
$Comp
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L GND #PWR065
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F 1 "GND" H 9950 3200 50 0000 C CNN
F 2 "" H 9950 3350 50 0001 C CNN
F 3 "" H 9950 3350 50 0001 C CNN
......@@ -2508,10 +2508,10 @@ Connection ~ 3450 4450
Wire Wire Line
3450 4100 3450 4050
$Comp
L 3V3_OUT #PWR0286
L 3V3_OUT #PWR066
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P 3450 4050
F 0 "#PWR0286" H 3450 3900 50 0001 C CNN
F 0 "#PWR066" H 3450 3900 50 0001 C CNN
F 1 "3V3_OUT" H 3450 4190 50 0000 C CNN
F 2 "" H 3450 4050 50 0001 C CNN
F 3 "" H 3450 4050 50 0001 C CNN
......@@ -2521,10 +2521,10 @@ $EndComp
Wire Wire Line
3800 5150 3800 5100
$Comp
L 3V3_OUT #PWR0287
L 3V3_OUT #PWR067
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P 3800 4050
F 0 "#PWR0287" H 3800 3900 50 0001 C CNN
F 0 "#PWR067" H 3800 3900 50 0001 C CNN
F 1 "3V3_OUT" H 3800 4190 50 0000 C CNN
F 2 "" H 3800 4050 50 0001 C CNN
F 3 "" H 3800 4050 50 0001 C CNN
......
......@@ -38,7 +38,7 @@ EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 5 24
Title "Librem5 development kit"
Title "Boot Configuration"
Date "2018-06-11"
Rev "v0.1.0"
Comp "Copyright 2018 GNU GPLv3"
......@@ -48,10 +48,10 @@ Comment3 "nicole.faerber@puri.sm"
Comment4 "christian.schilmoeller@puri.sm"
$EndDescr
$Comp
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L GND #PWR0123
U 1 1 5ACC0FBD
P 2050 3700
F 0 "#PWR047" H 2050 3450 50 0001 C CNN
F 0 "#PWR0123" H 2050 3450 50 0001 C CNN
F 1 "GND" H 2050 3550 50 0000 C CNN
F 2 "" H 2050 3700 50 0001 C CNN
F 3 "" H 2050 3700 50 0001 C CNN
......@@ -102,10 +102,10 @@ BOOT_CFG08
Text Label 7000 2250 0 60 ~ 0
BOOT_CFG09
$Comp
L GND #PWR048
L GND #PWR0124
U 1 1 5ACD1FAC
P 6600 2300
F 0 "#PWR048" H 6600 2050 50 0001 C CNN
F 0 "#PWR0124" H 6600 2050 50 0001 C CNN
F 1 "GND" H 6600 2150 50 0000 C CNN
F 2 "" H 6600 2300 50 0001 C CNN
F 3 "" H 6600 2300 50 0001 C CNN
......@@ -119,10 +119,10 @@ BOOT_CFG14
Text Label 7000 6050 0 60 ~ 0
BOOT_CFG15
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L GND #PWR049
L GND #PWR0125
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F 0 "#PWR0125" H 6600 5850 50 0001 C CNN
F 1 "GND" H 6600 5950 50 0000 C CNN
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F 3 "" H 6600 6100 50 0001 C CNN
......@@ -166,10 +166,10 @@ BOOT_MODE0
Text HLabel 2750 5200 0 60 Output ~ 0
BOOT_MODE1
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......@@ -178,7 +178,7 @@ F 3 "" H 3450 5800 50 0001 C CNN
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......@@ -536,7 +536,7 @@ EndData
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......@@ -2235,10 +2235,10 @@ F 9 "https://www.digikey.com/products/en/switches/slide-switches/213?FV=2080004%
0 -1 -1 0
$EndComp
$Comp
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L GND #PWR0127
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F 1 "GND" H 6600 3350 50 0000 C CNN
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......@@ -2253,10 +2253,10 @@ Wire Wire Line
6650 3450 6600 3450
Connection ~ 6600 3450
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......@@ -2268,10 +2268,10 @@ Wire Wire Line
Wire Wire Line
6600 4350 6650 4350
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......@@ -2299,10 +2299,10 @@ Wire Notes Line
Wire Notes Line
5300 6100 1600 6100
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......@@ -2310,10 +2310,10 @@ F 3 "" H 3550 4050 50 0001 C CNN
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......@@ -2343,10 +2343,10 @@ F 3 "" H 3000 2150 50 0001 C CNN
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......@@ -2361,10 +2361,10 @@ Connection ~ 2850 1950
Wire Wire Line
3000 2300 3000 2350
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......@@ -2414,4 +2414,6 @@ F 9 "https://octopart.com/search?q=ESD5B5.0ST1G&start=0" V 4200 5500 60 0001 C
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Text Notes 2300 4950 0 60 ~ 0
Note:\nAll switches' pins\ncan be swapped\ne.g. 2<->3\n or 1<->3\n (+BOOT_MODE2)
Text Notes 4250 1250 0 236 ~ 47
Boot Config
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......@@ -38,7 +38,7 @@ EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 14 24
Title "Librem5 development kit"
Title "Buttons & LED"
Date "2018-06-11"
Rev "v0.1.0"
Comp "Copyright 2018 GNU GPLv3"
......@@ -88,10 +88,10 @@ Wire Wire Line
Wire Wire Line
2850 3500 3000 3500
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......@@ -103,10 +103,10 @@ Wire Wire Line
Wire Wire Line
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Wire Wire Line
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......@@ -137,10 +137,10 @@ ON/OFF
Wire Wire Line
3400 6000 4300 6000
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......@@ -177,10 +177,10 @@ GP_LED1
Text Notes 9100 3400 0 60 ~ 0
LTST-C19HE1WT\n RBG Option
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......@@ -204,10 +204,10 @@ Wire Wire Line
Wire Wire Line
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......@@ -297,10 +297,10 @@ F 3 "" H 3650 3700 50 0001 C CNN
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$EndComp
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......@@ -325,10 +325,10 @@ F 3 "" H 3650 2450 50 0001 C CNN
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$EndComp
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......@@ -353,10 +353,10 @@ F 3 "" H 3650 6200 50 0001 C CNN
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......@@ -378,10 +378,10 @@ F 3 "" H 3650 4950 50 0001 C CNN
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~~4mA
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Buttons & LED
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......@@ -38,7 +38,7 @@ EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 13 24
Title "Librem5 development kit"
Title "MIPI CSI"
Date "2018-06-11"
Rev "v0.1.0"
Comp "Copyright 2018 GNU GPLv3"
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Using Internal DVDD 1.5V Regulator:
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2.7 POWER UP SEQUENCE\nBased on the system power configuration (1.8V or 2.8V for I/O power, using external\nDVDD or internal DVDD, requiring access to the I2C during power up period or not),\nthe power up sequence will differ. If 1.8V is used for I/O power, using the internal\nDVDD is preferred. If 2.8V is used for I/O power, due to a high voltage drop at the\ninternal DVDD regulator, there is a potential heat issue. Hence, for a 2.8V power\nsystem, OmniVision recommends using an external DVDD source. Due to the higher power\ndown current when using an external DVDD source, OmniVision strongly recommends\ncutting off all powers, including the external DVDD, when the sensor is not in use\nin the case of 2.8V I/O and external\nDVDD.\n2.7.1 POWER UP WITH INTERNAL DVDD\nFor powering up with the internal DVDD and I2C access during the power ON period, the\nfollowing conditions must occur:\n1. when DOVDD and AVDD are turned ON, make sure DOVDD becomes stable before AVDD becomes stable\n2. PWDN is active high with an asynchronized design (does not need clock)\n3. PWDN pin tied to digital ground if it is not controlled.\n4. if PWDN pin is controlled as below, for PWDN to go low, power must first become stable\n(AVDD to PWDN ≥ 5 ms)\n5. RESETB is active low with an asynchronized design\n6. master clock XVCLK should provide at least 1 ms before host accesses the sensor’s registers\n7. host can access I2C bus (if shared) during entire period. 20ms after RESETB goes high,\nhost can access the sensor's registers to initialize sensor
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