Commit 456a509a authored by Eric Kuzmenko's avatar Eric Kuzmenko

Replace WWAN M.2 circuit with one intended for mPCIe modules, include...

Replace WWAN M.2 circuit with one intended for mPCIe modules, include 74LVC1G08 single 2-input AND gate, create the AND gate's footprint and use the official SOT-23-5 3D model

The mini-SIM slot will need to be replaced with one that has an active-LOW detection pin. Will want to see if we can find cheap electrolytic to replace a few of the tantalum caps with (not all since we still need some low ESR, high capacitance, low profile, caps).
parent 10c9c210
......@@ -454,7 +454,7 @@ Text Notes 10000 2150 0 60 ~ 0
CTIA/AHJ
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-37dB=14.1254mV/Pa\n∴ mic produces 14.1254mVrms when exposed to a\n 1kHz tone of 94dB-SPL at the capsule\n (or 19.98mV amplitude)
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SMD Equivalent:\nSJ-43515RS-SMT-TR
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......
......@@ -51,7 +51,7 @@ Text Notes 1050 950 0 60 ~ 0
Using Internal DVDD 1.5V Regulator:
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......@@ -2857,7 +2857,7 @@ Text Notes 500 5150 0 60 ~ 0
2.7 POWER UP SEQUENCE\nBased on the system power configuration (1.8V or 2.8V for I/O power, using external\nDVDD or internal DVDD, requiring access to the I2C during power up period or not),\nthe power up sequence will differ. If 1.8V is used for I/O power, using the internal\nDVDD is preferred. If 2.8V is used for I/O power, due to a high voltage drop at the\ninternal DVDD regulator, there is a potential heat issue. Hence, for a 2.8V power\nsystem, OmniVision recommends using an external DVDD source. Due to the higher power\ndown current when using an external DVDD source, OmniVision strongly recommends\ncutting off all powers, including the external DVDD, when the sensor is not in use\nin the case of 2.8V I/O and external\nDVDD.\n2.7.1 POWER UP WITH INTERNAL DVDD\nFor powering up with the internal DVDD and I2C access during the power ON period, the\nfollowing conditions must occur:\n1. when DOVDD and AVDD are turned ON, make sure DOVDD becomes stable before AVDD becomes stable\n2. PWDN is active high with an asynchronized design (does not need clock)\n3. PWDN pin tied to digital ground if it is not controlled.\n4. if PWDN pin is controlled as below, for PWDN to go low, power must first become stable\n(AVDD to PWDN ≥ 5 ms)\n5. RESETB is active low with an asynchronized design\n6. master clock XVCLK should provide at least 1 ms before host accesses the sensor’s registers\n7. host can access I2C bus (if shared) during entire period. 20ms after RESETB goes high,\nhost can access the sensor's registers to initialize sensor
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Cap-Touch Controller IC PN:\n Goodix GT5688
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Backlight Array:
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......@@ -1705,7 +1705,7 @@ Wire Notes Line
5300 3950 4450 3950
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......@@ -2084,7 +2084,7 @@ Text Notes 1250 5200 0 60 ~ 0
Every time you power on or reset, you need\nto use the INT pin to set the I2C address:
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7-bit Slave Address: 0x5D\n (1011 101x)
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......
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......@@ -40,6 +40,11 @@ D Dual And2
K TTL and2
$ENDCMP
#
$CMP 74LVC1G08
D Single And2
K TTL and2
$ENDCMP
#
$CMP 74LVC1G32
D Single Or 2 inputs
K TTL Or2
......
......@@ -40,6 +40,11 @@ D Dual And2
K TTL and2
$ENDCMP
#
$CMP 74LVC1G08
D Single And2
K TTL and2
$ENDCMP
#
$CMP 74LVC1G32
D Single Or 2 inputs
K TTL Or2
......
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No preview for this file type
(module 74LVC1G08 (layer F.Cu) (tedit 5B2B4889)
(descr https://www.nxp.com/docs/en/package-information/SOT753.pdf)
(tags 74LVC1G08)
(solder_mask_margin 0.05)
(solder_paste_margin -0.05)
(attr smd)
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(effects (font (size 1 1) (thickness 0.15)))
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(pad 1 smd rect (at -1.2 -0.95) (size 0.8 0.55) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -1.2 0) (size 0.8 0.55) (layers F.Cu F.Paste F.Mask))
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(pad 5 smd rect (at 1.2 -0.95) (size 0.8 0.55) (layers F.Cu F.Paste F.Mask))
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update=Di 19 Jun 2018 14:44:55 CEST
update=Thu 21 Jun 2018 02:47:16 AM EDT
version=1
last_client=kicad
[cvpcb]
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SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[general]
version=1
[pcbnew]
version=1
PageLayoutDescrFile=purism_portrait.kicad_wks
......@@ -72,3 +70,5 @@ LibName30=atmel
LibName31=contrib
LibName32=valves
LibName33=dvk-mx8m-bsb
[general]
version=1
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......@@ -172,7 +172,7 @@ F 9 "https://www.mouser.com/Connectors/Memory-Connectors/Memory-Card-Connectors/
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SDO_A/G Address\n 1 0x6B\n 0 0x6A
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6.2 M.2 Signal Directions
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......
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