added .gitignore (avoid *.bak files in git)

added library symbol and footprint of minipcie socket for later use
parent 8ccb026e
*.bak
*cache.*
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EESchema-DOCLIB Version 2.0
#
#End Doc Library
EESchema-DOCLIB Version 2.0
#
#End Doc Library
This diff is collapsed.
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......@@ -2178,4 +2178,71 @@ X VCI_TP_VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#
# MPCIE-Socket
#
DEF MPCIE-Socket U 0 40 Y Y 1 F N
F0 "U" -400 1300 60 H V C CNN
F1 "MPCIE-Socket" 100 -1550 60 H V C CNN
F2 "" 100 -1000 60 H V C CNN
F3 "" 100 -1000 60 H V C CNN
DRAW
T 0 0 -650 60 0 0 0 Mechanical~Key Normal 0 C C
S -450 -1500 450 1250 0 1 0 N
S -450 -600 450 -700 0 1 0 N
X ~WAKE 1 -650 -1450 200 R 50 50 1 1 B
X +3.3Vaux 2 650 -1450 200 L 50 50 1 1 W X
X COEX1 3 -650 -1350 200 R 50 50 1 1 B
X GND 4 650 -1350 200 L 50 50 1 1 W X
X COEX2 5 -650 -1250 200 R 50 50 1 1 B
X +1.5V 6 650 -1250 200 L 50 50 1 1 W X
X ~CLKREQ 7 -650 -1150 200 R 50 50 1 1 B
X UIM_PWR 8 650 -1150 200 L 50 50 1 1 B
X GND 9 -650 -1050 200 R 50 50 1 1 W X
X UIM_DATA 10 650 -1050 200 L 50 50 1 1 B
X ~W_DISABLE 20 650 -450 200 L 50 50 1 1 B I
X SMB_CLK 30 650 50 200 L 50 50 1 1 B C
X GND 40 650 550 200 L 50 50 1 1 W X
X GND 50 650 1050 200 L 50 50 1 1 W X
X RefClk- 11 -650 -950 200 R 50 50 1 1 I C
X GND 21 -650 -350 200 R 50 50 1 1 W X
X PETn0 31 -650 150 200 R 50 50 1 1 B
X +3.3Aux 41 -650 650 200 R 50 50 1 1 W X
X Reserved 51 -650 1150 200 R 50 50 1 1 N
X UIM_CLK 12 650 -950 200 L 50 50 1 1 B C
X ~PERST 22 650 -350 200 L 50 50 1 1 B I
X SMB_DATA 32 650 150 200 L 50 50 1 1 B
X ~LED_WWAN 42 650 650 200 L 50 50 1 1 B I
X +3.3Vaux 52 650 1150 200 L 50 50 1 1 W X
X RefClk+ 13 -650 -850 200 R 50 50 1 1 I C
X PERn0 23 -650 -250 200 R 50 50 1 1 B
X PETp0 33 -650 250 200 R 50 50 1 1 B
X GND 43 -650 750 200 R 50 50 1 1 W X
X UIM_RESET 14 650 -850 200 L 50 50 1 1 B
X +3.3Vaux 24 650 -250 200 L 50 50 1 1 W X
X GND 34 650 250 200 L 50 50 1 1 W X
X ~LED_WLAN 44 650 750 200 L 50 50 1 1 B I
X GND 15 -650 -750 200 R 50 50 1 1 W X
X PERp0 25 -650 -150 200 R 50 50 1 1 B
X GND 35 -650 350 200 R 50 50 1 1 W X
X Reserved 45 -650 850 200 R 50 50 1 1 N
X UIM_VPP 16 650 -750 200 L 50 50 1 1 B
X GND 26 650 -150 200 L 50 50 1 1 W X
X USB_D- 36 650 350 200 L 50 50 1 1 B
X ~LED_WPAN 46 650 850 200 L 50 50 1 1 B I
X UIM_C8 17 -650 -550 200 R 50 50 1 1 B
X GND 27 -650 -50 200 R 50 50 1 1 W X
X GND 37 -650 450 200 R 50 50 1 1 W X
X Reserved 47 -650 950 200 R 50 50 1 1 N
X GND 18 650 -550 200 L 50 50 1 1 W X
X +1.5V 28 650 -50 200 L 50 50 1 1 W X
X USB_D+ 38 650 450 200 L 50 50 1 1 B
X +1.5V 48 650 950 200 L 50 50 1 1 W X
X UIM_C4 19 -650 -450 200 R 50 50 1 1 B
X GND 29 -650 50 200 R 50 50 1 1 W X
X +3.3Aux 39 -650 550 200 R 50 50 1 1 W X
X Reserved 49 -650 1050 200 R 50 50 1 1 N
ENDDRAW
ENDDEF
#
#End Library
(module mpcie-socket (layer F.Cu) (tedit 541E6573)
(tags "mpci, pci, pci express")
(fp_text reference Ref** (at 30.45 2.45 90) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_text value Val** (at 30.35 -4.2 90) (layer F.SilkS)
(effects (font (thickness 0.15)))
)
(fp_line (start -2.5 -50.95) (end 3.3 -50.95) (layer Dwgs.User) (width 0.05))
(fp_line (start 3.3 -50.95) (end 3.3 -45.15) (layer Dwgs.User) (width 0.05))
(fp_line (start -2.5 -45.15) (end 3.3 -45.15) (layer Dwgs.User) (width 0.05))
(fp_line (start -2.5 -50.95) (end -2.5 -45.15) (layer Dwgs.User) (width 0.05))
(fp_line (start 21.7 -50.95) (end 21.7 -45.15) (layer Dwgs.User) (width 0.05))
(fp_line (start 21.7 -45.15) (end 27.5 -45.15) (layer Dwgs.User) (width 0.05))
(fp_line (start 27.5 -50.95) (end 27.5 -45.15) (layer Dwgs.User) (width 0.05))
(fp_line (start 21.7 -50.95) (end 27.5 -50.95) (layer Dwgs.User) (width 0.05))
(fp_line (start 3.3 -22.7) (end 3.3 -26.8) (layer Dwgs.User) (width 0.05))
(fp_line (start -2.5 -21) (end 1.6 -21) (layer Dwgs.User) (width 0.05))
(fp_line (start -2.5 -26.8) (end -2.5 -21) (layer Dwgs.User) (width 0.05))
(fp_line (start 3.3 -26.8) (end -2.5 -26.8) (layer Dwgs.User) (width 0.05))
(fp_line (start 3.3 -22.7) (end 1.6 -21) (layer Dwgs.User) (width 0.05))
(fp_line (start 21.7 -22.7) (end 23.4 -21) (layer Dwgs.User) (width 0.05))
(fp_line (start -3.55 5.75) (end 28.55 5.75) (layer F.SilkS) (width 0.5))
(fp_line (start 28.95 5.35) (end 28.95 -5.35) (layer F.SilkS) (width 0.5))
(fp_line (start 28.55 -5.75) (end -3.55 -5.75) (layer F.SilkS) (width 0.5))
(fp_line (start -3.95 -5.35) (end -3.95 5.35) (layer F.SilkS) (width 0.5))
(fp_line (start 8.65 4.1) (end 8.65 -4.1) (layer Dwgs.User) (width 0.01))
(fp_line (start 21.7 -26.8) (end 27.5 -26.8) (layer Dwgs.User) (width 0.05))
(fp_line (start 27.5 -26.8) (end 27.5 -21) (layer Dwgs.User) (width 0.05))
(fp_line (start 27.5 -21) (end 23.4 -21) (layer Dwgs.User) (width 0.05))
(fp_line (start 21.7 -22.7) (end 21.7 -26.8) (layer Dwgs.User) (width 0.05))
(fp_line (start 0 -50.95) (end 0 5.1) (layer Dwgs.User) (width 0.01))
(fp_line (start -3.3 0) (end 28.225 0) (layer Dwgs.User) (width 0.01))
(pad "" connect circle (at 25 0) (size 1.05 1.05) (layers F.SilkS Dwgs.User))
(pad "" connect circle (at 0 0) (size 1.6 1.6) (layers F.SilkS Dwgs.User))
(pad "" smd rect (at -2.15 3.5) (size 2.3 3.2) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at 27.15 3.5) (size 2.3 3.2) (layers F.Cu F.Paste F.Mask))
(pad "" connect rect (at 0.4 -23.9) (size 5.8 5.8) (layers F.SilkS))
(pad "" connect rect (at 0.4 -48.05) (size 5.8 5.8) (layers F.SilkS))
(pad "" connect rect (at 24.6 -48.05) (size 5.8 5.8) (layers F.SilkS))
(pad "" connect rect (at 24.6 -23.9) (size 5.8 5.8) (layers F.SilkS))
(pad 1 smd rect (at 0.7 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 1.1 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at 1.5 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at 1.9 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at 2.3 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at 2.7 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at 3.1 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at 3.5 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at 3.9 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at 4.3 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at 4.7 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at 5.1 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at 5.5 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at 5.9 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at 6.3 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 16 smd rect (at 6.7 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 17 smd rect (at 10.3 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 18 smd rect (at 10.7 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 19 smd rect (at 11.1 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 20 smd rect (at 11.5 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at 11.9 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 22 smd rect (at 12.3 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 23 smd rect (at 12.7 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 24 smd rect (at 13.1 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 25 smd rect (at 13.5 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 26 smd rect (at 13.9 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 27 smd rect (at 14.3 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 28 smd rect (at 14.7 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 29 smd rect (at 15.1 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 30 smd rect (at 15.5 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 31 smd rect (at 15.9 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 32 smd rect (at 16.3 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at 16.7 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 34 smd rect (at 17.1 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 35 smd rect (at 17.5 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 36 smd rect (at 17.9 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 37 smd rect (at 18.3 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 38 smd rect (at 18.7 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 39 smd rect (at 19.1 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 40 smd rect (at 19.5 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 41 smd rect (at 19.9 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 42 smd rect (at 20.3 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 43 smd rect (at 20.7 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 44 smd rect (at 21.1 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 45 smd rect (at 21.5 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 46 smd rect (at 21.9 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 47 smd rect (at 22.3 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 48 smd rect (at 22.7 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 49 smd rect (at 23.1 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 50 smd rect (at 23.5 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 51 smd rect (at 23.9 4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
(pad 52 smd rect (at 24.3 -4.1) (size 0.6 2) (layers F.Cu F.Paste F.Mask))
)
update=Mon 30 Apr 2018 07:54:26 PM EDT
update=Mi 02 Mai 2018 15:11:34 CEST
version=1
last_client=kicad
[pcbnew]
......@@ -23,6 +23,8 @@ ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[eeschema]
version=1
LibDir=
......@@ -60,5 +62,3 @@ LibName30=atmel
LibName31=contrib
LibName32=valves
LibName33=dvk-mx8m-bsb
[general]
version=1
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:switches
LIBS:relays
LIBS:motors
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:dvk-mx8m-bsb
LIBS:dvk-mx8m-bsb-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 7 15
Title "JTAG"
Date "2018-05-02"
Rev "v0.1.0"
Comp "Purism SPC"
Comment1 "Copyright 2018"
Comment2 "GNU GPLv3"
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Conn_02x05_Odd_Even J801
U 1 1 5AD052A0
P 6150 3550
F 0 "J801" H 6200 3850 50 0000 C CNN
F 1 "NC" H 6200 3250 50 0000 C CNN
F 2 "" H 6150 3550 50 0001 C CNN
F 3 "https://media.digikey.com/pdf/Data%20Sheets/Sullins%20PDFs/GRPB_%20_2VWQS-RC%2010958-C.pdf" H 6150 3550 50 0001 C CNN
F 4 "Sullins" H 6150 3550 60 0001 C CNN "MFG Name"
F 5 "GRPB052VWQS-RC" H 6150 3550 60 0001 C CNN "MFG Part Num"
F 6 "S9012E-05-ND" H 6150 3550 60 0001 C CNN "Distrib PN"
F 7 "https://www.digikey.com/product-detail/en/sullins-connector-solutions/GRPB052VWQS-RC/S9012E-05-ND/1786414" H 6150 3550 60 0001 C CNN "Distrib Link"
F 8 "-" H 6150 3550 60 0001 C CNN "Tolerance"
F 9 "https://www.digikey.com/products/en/connectors-interconnects/rectangular-connectors-headers-male-pins/314?k=&pkeyword=&pv2024=6&FV=1140003%2C160000a%2C1680002%2C1fa40016%2Cffe0013a&quantity=0&ColumnSort=1000011&page=1&pageSize=500" H 6150 3550 60 0001 C CNN "Others"
1 6150 3550
-1 0 0 -1
$EndComp
$Comp
L R R804
U 1 1 5AD052F0
P 6700 3650
F 0 "R804" V 6750 3850 50 0000 C CNN
F 1 "NC" V 6700 3650 50 0000 C CNN
F 2 "" V 6630 3650 50 0001 C CNN
F 3 "" H 6700 3650 50 0001 C CNN
1 6700 3650
0 -1 -1 0
$EndComp
$Comp
L R R805
U 1 1 5AD0530D
P 6700 3750
F 0 "R805" V 6780 3750 50 0000 C CNN
F 1 "0" V 6700 3750 50 0000 C CNN
F 2 "" V 6630 3750 50 0001 C CNN
F 3 "" H 6700 3750 50 0001 C CNN
1 6700 3750
0 1 1 0
$EndComp
$Comp
L R R802
U 1 1 5AD058A3
P 6100 3950
F 0 "R802" V 6180 3950 50 0000 C CNN
F 1 "NC" V 6100 3950 50 0000 C CNN
F 2 "" V 6030 3950 50 0001 C CNN
F 3 "" H 6100 3950 50 0001 C CNN
1 6100 3950
0 1 1 0
$EndComp
$Comp
L D_Schottky D801
U 1 1 5AD05906
P 5500 3750
F 0 "D801" H 5500 3850 50 0000 C CNN
F 1 "CFSH05-20L" H 5825 3700 50 0000 C CNN
F 2 "" H 5500 3750 50 0001 C CNN
F 3 "" H 5500 3750 50 0001 C CNN
1 5500 3750
-1 0 0 1
$EndComp
$Comp
L R R803
U 1 1 5AD0593B
P 6400 3150
F 0 "R803" H 6250 3100 50 0000 C CNN
F 1 "120" H 6275 3200 50 0000 C CNN
F 2 "" V 6330 3150 50 0001 C CNN
F 3 "" H 6400 3150 50 0001 C CNN
1 6400 3150
-1 0 0 1
$EndComp
Wire Wire Line
6350 3350 6400 3350
Wire Wire Line
6400 3350 6400 3300
Wire Wire Line
6400 3000 6400 2950
Wire Wire Line
6350 3650 6550 3650
Wire Wire Line
6350 3750 6550 3750
Wire Wire Line
6250 3950 6500 3950
Wire Wire Line
6500 3950 6500 3750
Connection ~ 6500 3750
$Comp
L GND #PWR0109
U 1 1 5AD06B94
P 6900 3800
F 0 "#PWR0109" H 6900 3550 50 0001 C CNN
F 1 "GND" H 6900 3650 50 0000 C CNN
F 2 "" H 6900 3800 50 0001 C CNN
F 3 "" H 6900 3800 50 0001 C CNN
1 6900 3800
1 0 0 -1
$EndComp
Wire Wire Line
6350 3450 6900 3450
Wire Wire Line
6900 3450 6900 3800
Wire Wire Line
6350 3550 6900 3550
Connection ~ 6900 3550
Wire Wire Line
6850 3650 6900 3650
Connection ~ 6900 3650
Wire Wire Line
6850 3750 6900 3750
Connection ~ 6900 3750
$Comp
L R R801
U 1 1 5AD07568
P 5700 4150
F 0 "R801" H 5850 4200 50 0000 C CNN
F 1 "10k" H 5825 4100 50 0000 C CNN
F 2 "" V 5630 4150 50 0001 C CNN
F 3 "" H 5700 4150 50 0001 C CNN
1 5700 4150
1 0 0 -1
$EndComp
Wire Wire Line
4900 3450 5850 3450
Wire Wire Line
5700 3450 5700 4000
$Comp
L GND #PWR0110
U 1 1 5AD075E7
P 5700 4350
F 0 "#PWR0110" H 5700 4100 50 0001 C CNN
F 1 "GND" H 5700 4200 50 0000 C CNN
F 2 "" H 5700 4350 50 0001 C CNN
F 3 "" H 5700 4350 50 0001 C CNN
1 5700 4350
1 0 0 -1
$EndComp
Wire Wire Line
5700 4350 5700 4300
Text HLabel 4900 3350 0 60 Output ~ 0
JTAG_TMS
Text HLabel 4900 3450 0 60 Output ~ 0
JTAG_TCK
Text HLabel 4900 3550 0 60 Input ~ 0
JTAG_TDO
Text HLabel 4900 3650 0 60 Output ~ 0
JTAG_TDI
Text HLabel 4900 3750 0 60 Output ~ 0
POR_B
Wire Wire Line
4900 3350 5850 3350
Connection ~ 5700 3450
Wire Wire Line
4900 3550 5850 3550
Wire Wire Line
4900 3650 5850 3650
Wire Wire Line
4900 3750 5350 3750
Wire Wire Line
5650 3750 5850 3750
Wire Wire Line
5950 3950 4900 3950
Text HLabel 4900 3950 0 60 Output ~ 0
JTAG_~TRST
Text Notes 5700 3200 0 60 ~ 0
ARM DStream
$Comp
L 3V3_OUT #PWR0111
U 1 1 5AEA3F80
P 6400 2950
F 0 "#PWR0111" H 6400 2800 50 0001 C CNN
F 1 "3V3_OUT" H 6400 3090 50 0000 C CNN
F 2 "" H 6400 2950 50 0001 C CNN
F 3 "" H 6400 2950 50 0001 C CNN
1 6400 2950
1 0 0 -1
$EndComp
$Comp
L R R806
U 1 1 5AE57347
P 5200 3150
F 0 "R806" H 5350 3200 50 0000 C CNN
F 1 "10k" H 5325 3100 50 0000 C CNN
F 2 "" V 5130 3150 50 0001 C CNN
F 3 "" H 5200 3150 50 0001 C CNN
1 5200 3150
-1 0 0 -1
$EndComp
$Comp
L R R807
U 1 1 5AE5736E
P 5300 3150
F 0 "R807" H 5450 3200 50 0000 C CNN
F 1 "10k" H 5425 3100 50 0000 C CNN
F 2 "" V 5230 3150 50 0001 C CNN
F 3 "" H 5300 3150 50 0001 C CNN
1 5300 3150
1 0 0 -1
$EndComp
$Comp
L 3V3_OUT #PWR0112
U 1 1 5AE5744F
P 5250 2900
F 0 "#PWR0112" H 5250 2750 50 0001 C CNN
F 1 "3V3_OUT" H 5250 3040 50 0000 C CNN
F 2 "" H 5250 2900 50 0001 C CNN
F 3 "" H 5250 2900 50 0001 C CNN
1 5250 2900
1 0 0 -1
$EndComp
Wire Wire Line
5200 3000 5200 2950
Wire Wire Line
5200 2950 5300 2950
Wire Wire Line
5300 2950 5300 3000
Wire Wire Line
5250 2950 5250 2900
Connection ~ 5250 2950
Wire Wire Line
5200 3300 5200 3350
Connection ~ 5200 3350
Wire Wire Line
5300 3300 5300 3650
Connection ~ 5300 3650
$EndSCHEMATC
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