Commit 616433a7 authored by Bob Ham's avatar Bob Ham
Browse files

Merge branch 'imx8-4.18-drop-dpu' into 'imx8-4.18-wip'

Drop DPU related bits

See merge request !26
parents 6155516c 087e3ad5
Pipeline #8436 passed with stage
in 47 minutes and 30 seconds
config IMX8_PRG
tristate
default y if IMX_DPU_CORE=y
default m if IMX_DPU_CORE=m
config IMX8_DPRC
tristate
default y if IMX_DPU_CORE=y
default m if IMX_DPU_CORE=m
source drivers/gpu/imx/dpu/Kconfig
source drivers/gpu/imx/dpu-blit/Kconfig
source drivers/gpu/imx/dcss/Kconfig
obj-$(CONFIG_IMX8_PRG) += imx8_prg.o
obj-$(CONFIG_IMX8_DPRC) += imx8_dprc.o
obj-$(CONFIG_IMX_DPU_CORE) += dpu/
obj-$(CONFIG_IMX_DPU_BLIT) += dpu-blit/
obj-$(CONFIG_IMX_DCSS_CORE) += dcss/
config IMX_DPU_BLIT
tristate
depends on IMX_DPU_CORE
default y if IMX_DPU_CORE=y
default m if IMX_DPU_CORE=m
ccflags-y += -Idrivers/gpu/imx/dpu
imx-dpu-blit-objs := dpu-blit.o
obj-$(CONFIG_IMX_DPU_BLIT) += imx-dpu-blit.o
/*
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef __DPU_BLIT_REGISTERS_H__
#define __DPU_BLIT_REGISTERS_H__
/* Registers Defination */
#define COMCTRL_IPIDENTIFIER ((uint32_t)(0))
#define PIXENGCFG_STORE9_TRIGGER ((uint32_t)(0x954))
#define COMCTRL_USERINTERRUPTMASK0 ((uint32_t)(0x48))
#define COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK 0xFFFFFFFFU
#define COMCTRL_USERINTERRUPTENABLE0 ((uint32_t)(0x80))
#define COMCTRL_INTERRUPTENABLE0 ((uint32_t)(0x50))
#define COMCTRL_INTERRUPTSTATUS0 ((uint32_t)(0x68))
#define COMCTRL_USERINTERRUPTSTATUS0 ((uint32_t)(0x98))
#define COMCTRL_USERINTERRUPTCLEAR0 ((uint32_t)(0x90))
#define COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_MASK 0xFFFFFFFFU
#define COMCTRL_INTERRUPTCLEAR0 ((uint32_t)(0x60))
#define COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_MASK 0xFFFFFFFFU
#define PIXENGCFG_FETCHDECODE9_DYNAMIC ((uint32_t)(0x828))
#define PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_VALUE 0U
#define PIXENGCFG_FETCHWARP9_DYNAMIC ((uint32_t)(0x848))
#define PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_VALUE 0U
#define PIXENGCFG_ROP9_DYNAMIC ((uint32_t)(0x868))
#define PIXENGCFG_ROP9_DYNAMIC_RESET_VALUE 0x1000000U
#define PIXENGCFG_MATRIX9_DYNAMIC ((uint32_t)(0x8A8))
#define PIXENGCFG_MATRIX9_DYNAMIC_RESET_VALUE 0x1000000U
#define PIXENGCFG_HSCALER9_DYNAMIC ((uint32_t)(0x8C8))
#define PIXENGCFG_HSCALER9_DYNAMIC_RESET_VALUE 0x1000000U
#define PIXENGCFG_VSCALER9_DYNAMIC ((uint32_t)(0x8E8))
#define PIXENGCFG_VSCALER9_DYNAMIC_RESET_VALUE 0x1000000U
#define PIXENGCFG_BLITBLEND9_DYNAMIC ((uint32_t)(0x928))
#define PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_VALUE 0x1000000U
#define PIXENGCFG_STORE9_STATIC ((uint32_t)(0x948))
#define PIXENGCFG_STORE9_STATIC_RESET_VALUE 0x800010U
#define PIXENGCFG_STORE9_STATIC_RESET_MASK 0xFFFFFFFFU
#define PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_MASK 0x1U
#define PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_SHIFT 0U
#define PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_MASK 0x10U
#define PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_SHIFT 4U
#define PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_MASK 0x100U
#define PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_SHIFT 8U
#define PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE 0U
#define PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__AUTO 0x1U
#define PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_MASK 0x800U
#define PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_SHIFT 11U
/* Field Value: STORE9_SW_RESET__OPERATION, Normal Operation */
#define PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION 0U
/* Field Value: STORE9_SW_RESET__SWRESET, Software Reset */
#define PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__SWRESET 0x1U
#define PIXENGCFG_STORE9_STATIC_STORE9_DIV_MASK 0xFF0000U
#define PIXENGCFG_STORE9_STATIC_STORE9_DIV_SHIFT 16U
#define PIXENGCFG_STORE9_DYNAMIC ((uint32_t)(0x94C))
#define FETCHDECODE9_STATICCONTROL ((uint32_t)(0x1008))
#define FETCHDECODE9_STATICCONTROL_OFFSET ((uint32_t)(0x8))
#define FETCHDECODE9_STATICCONTROL_RESET_VALUE 0U
#define FETCHDECODE9_STATICCONTROL_SHDEN_MASK 0x1U
#define FETCHDECODE9_STATICCONTROL_SHDEN_SHIFT 0U
#define FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
#define FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
#define FETCHDECODE9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x100C))
#define FETCHDECODE9_BASEADDRESS0 ((uint32_t)(0x101C))
#define FETCHDECODE9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1020))
#define FETCHDECODE9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1024))
#define FETCHDECODE9_COLORCOMPONENTBITS0 ((uint32_t)(0x1028))
#define FETCHDECODE9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x102C))
#define FETCHDECODE9_LAYEROFFSET0 ((uint32_t)(0x1030))
#define FETCHDECODE9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1034))
#define FETCHDECODE9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x1038))
#define FETCHDECODE9_CONSTANTCOLOR0 ((uint32_t)(0x103C))
#define FETCHDECODE9_LAYERPROPERTY0 ((uint32_t)(0x1040))
#define FETCHDECODE9_FRAMEDIMENSIONS ((uint32_t)(0x1044))
#define FETCHDECODE9_FRAMERESAMPLING ((uint32_t)(0x1048))
#define FETCHDECODE9_CONTROL ((uint32_t)(0x1054))
#define FETCHWARP9_STATICCONTROL ((uint32_t)(0x1808))
#define FETCHWARP9_STATICCONTROL_OFFSET ((uint32_t)(0x8))
#define FETCHWARP9_STATICCONTROL_RESET_VALUE 0xFF000000U
#define FETCHWARP9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU
#define FETCHWARP9_STATICCONTROL_SHDEN_MASK 0x1U
#define FETCHWARP9_STATICCONTROL_SHDEN_SHIFT 0U
#define FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
#define FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
#define FETCHWARP9_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U
#define FETCHWARP9_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U
#define FETCHWARP9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x180C))
#define FETCHWARP9_BASEADDRESS0 ((uint32_t)(0x1810))
#define FETCHWARP9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1814))
#define FETCHWARP9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1818))
#define FETCHWARP9_COLORCOMPONENTBITS0 ((uint32_t)(0x181C))
#define FETCHWARP9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x1820))
#define FETCHWARP9_LAYEROFFSET0 ((uint32_t)(0x1824))
#define FETCHWARP9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1828))
#define FETCHWARP9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x182C))
#define FETCHWARP9_CONSTANTCOLOR0 ((uint32_t)(0x1830))
#define FETCHWARP9_LAYERPROPERTY0 ((uint32_t)(0x1834))
#define FETCHWARP9_FRAMEDIMENSIONS ((uint32_t)(0x1950))
#define FETCHWARP9_FRAMERESAMPLING ((uint32_t)(0x1954))
#define FETCHWARP9_CONTROL ((uint32_t)(0x1970))
#define FETCHECO9_STATICCONTROL ((uint32_t)(0x1C08))
#define FETCHECO9_STATICCONTROL_OFFSET ((uint32_t)(0x8))
#define FETCHECO9_STATICCONTROL_RESET_VALUE 0U
#define FETCHECO9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU
#define FETCHECO9_STATICCONTROL_SHDEN_MASK 0x1U
#define FETCHECO9_STATICCONTROL_SHDEN_SHIFT 0U
#define FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
#define FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
#define FETCHECO9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x1C0C))
#define FETCHECO9_BASEADDRESS0 ((uint32_t)(0x1C10))
#define FETCHECO9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1C14))
#define FETCHECO9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1C18))
#define FETCHECO9_COLORCOMPONENTBITS0 ((uint32_t)(0x1C1C))
#define FETCHECO9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x1C20))
#define FETCHECO9_LAYEROFFSET0 ((uint32_t)(0x1C24))
#define FETCHECO9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1C28))
#define FETCHECO9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x1C2C))
#define FETCHECO9_CONSTANTCOLOR0 ((uint32_t)(0x1C30))
#define FETCHECO9_LAYERPROPERTY0 ((uint32_t)(0x1C34))
#define FETCHECO9_FRAMEDIMENSIONS ((uint32_t)(0x1C38))
#define FETCHECO9_FRAMERESAMPLING ((uint32_t)(0x1C3C))
#define FETCHECO9_CONTROL ((uint32_t)(0x1C40))
#define ROP9_STATICCONTROL ((uint32_t)(0x2008))
#define ROP9_STATICCONTROL_OFFSET ((uint32_t)(0x8))
#define ROP9_STATICCONTROL_RESET_VALUE 0U
#define ROP9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU
#define ROP9_STATICCONTROL_SHDEN_MASK 0x1U
#define ROP9_STATICCONTROL_SHDEN_SHIFT 0U
#define ROP9_CONTROL ((uint32_t)(0x200C))
#define MATRIX9_STATICCONTROL ((uint32_t)(0x2C08))
#define MATRIX9_STATICCONTROL_OFFSET ((uint32_t)(0x8))
#define MATRIX9_STATICCONTROL_RESET_VALUE 0U
#define MATRIX9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU
#define MATRIX9_STATICCONTROL_SHDEN_MASK 0x1U
#define MATRIX9_STATICCONTROL_SHDEN_SHIFT 0U
#define MATRIX9_CONTROL ((uint32_t)(0x2C0C))
#define HSCALER9_SETUP1 ((uint32_t)(0x300C))
#define HSCALER9_SETUP2 ((uint32_t)(0x3010))
#define HSCALER9_CONTROL ((uint32_t)(0x3014))
#define VSCALER9_STATICCONTROL ((uint32_t)(0x3408))
#define VSCALER9_STATICCONTROL_OFFSET ((uint32_t)(0x8))
#define VSCALER9_STATICCONTROL_RESET_VALUE 0U
#define VSCALER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU
#define VSCALER9_STATICCONTROL_SHDEN_MASK 0x1U
#define VSCALER9_STATICCONTROL_SHDEN_SHIFT 0U
#define VSCALER9_SETUP1 ((uint32_t)(0x340C))
#define VSCALER9_SETUP2 ((uint32_t)(0x3410))
#define VSCALER9_SETUP3 ((uint32_t)(0x3414))
#define VSCALER9_SETUP4 ((uint32_t)(0x3418))
#define VSCALER9_SETUP5 ((uint32_t)(0x341C))
#define VSCALER9_CONTROL ((uint32_t)(0x3420))
#define HSCALER9_STATICCONTROL ((uint32_t)(0x3008))
#define HSCALER9_STATICCONTROL_OFFSET ((uint32_t)(0x8))
#define HSCALER9_STATICCONTROL_RESET_VALUE 0U
#define HSCALER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU
#define HSCALER9_STATICCONTROL_SHDEN_MASK 0x1U
#define HSCALER9_STATICCONTROL_SHDEN_SHIFT 0U
#define BLITBLEND9_STATICCONTROL ((uint32_t)(0x3C08))
#define BLITBLEND9_STATICCONTROL_OFFSET ((uint32_t)(0x8))
#define BLITBLEND9_STATICCONTROL_RESET_VALUE 0U
#define BLITBLEND9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU
#define BLITBLEND9_STATICCONTROL_SHDEN_MASK 0x1U
#define BLITBLEND9_STATICCONTROL_SHDEN_SHIFT 0U
#define BLITBLEND9_CONTROL ((uint32_t)(0x3C0C))
#define BLITBLEND9_CONSTANTCOLOR ((uint32_t)(0x3C14))
#define BLITBLEND9_COLORREDBLENDFUNCTION ((uint32_t)(0x3C18))
#define BLITBLEND9_COLORGREENBLENDFUNCTION ((uint32_t)(0x3C1C))
#define BLITBLEND9_COLORBLUEBLENDFUNCTION ((uint32_t)(0x3C20))
#define BLITBLEND9_ALPHABLENDFUNCTION ((uint32_t)(0x3C24))
#define BLITBLEND9_BLENDMODE1 ((uint32_t)(0x3C28))
#define BLITBLEND9_BLENDMODE2 ((uint32_t)(0x3C2C))
#define STORE9_STATICCONTROL ((uint32_t)(0x4008))
#define STORE9_STATICCONTROL_OFFSET ((uint32_t)(0x8))
#define STORE9_STATICCONTROL_RESET_VALUE 0U
#define STORE9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU
#define STORE9_STATICCONTROL_SHDEN_MASK 0x1U
#define STORE9_STATICCONTROL_SHDEN_SHIFT 0U
#define STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0x100U
#define STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 8U
#define STORE9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x400C))
#define STORE9_BASEADDRESS ((uint32_t)(0x4018))
#define STORE9_DESTINATIONBUFFERATTRIBUTES ((uint32_t)(0x401C))
#define STORE9_DESTINATIONBUFFERDIMENSION ((uint32_t)(0x4020))
#define STORE9_FRAMEOFFSET ((uint32_t)(0x4024))
#define STORE9_COLORCOMPONENTBITS ((uint32_t)(0x4028))
#define STORE9_COLORCOMPONENTSHIFT ((uint32_t)(0x402C))
#define STORE9_CONTROL ((uint32_t)(0x4030))
#define STORE9_START ((uint32_t)(0x403C))
/* pixengcfg */
#define PIXENGCFG_CLKEN_MASK 0x3000000U
#define PIXENGCFG_CLKEN_SHIFT 24U
/* Field Value: _CLKEN__DISABLE, Clock for block is disabled */
#define PIXENGCFG_CLKEN__DISABLE 0U
#define PIXENGCFG_CLKEN__AUTOMATIC 0x1U
/* Field Value: _CLKEN__FULL, Clock for block is without gating */
#define PIXENGCFG_CLKEN__FULL 0x3U
#define PIXENGCFG_DIVIDER_RESET 0x80
/* command sequencer */
#define CMDSEQ_HIF ((uint32_t)(0x400))
#define CMDSEQ_LOCKUNLOCKHIF ((uint32_t)(0x500))
#define CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNLOCK_KEY 0x691DB936U
#define CMDSEQ_LOCKUNLOCK ((uint32_t)(0x580))
#define CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
#define CMDSEQ_BUFFERADDRESS ((uint32_t)(0x588))
#define CMDSEQ_BUFFERSIZE ((uint32_t)(0x58C))
#define CMDSEQ_CONTROL ((uint32_t)(0x594))
#define CMDSEQ_CONTROL_OFFSET ((uint32_t)(0x194))
#define CMDSEQ_CONTROL_RESET_VALUE 0U
#define CMDSEQ_CONTROL_RESET_MASK 0xFFFFFFFFU
#define CMDSEQ_CONTROL_CLRAXIW_MASK 0x1U
#define CMDSEQ_CONTROL_CLRAXIW_SHIFT 0U
#define CMDSEQ_CONTROL_CLRRBUF_MASK 0x4U
#define CMDSEQ_CONTROL_CLRRBUF_SHIFT 2U
#define CMDSEQ_CONTROL_CLRCMDBUF_MASK 0x8U
#define CMDSEQ_CONTROL_CLRCMDBUF_SHIFT 3U
#define CMDSEQ_CONTROL_CLEAR_MASK 0x80000000U
#define CMDSEQ_CONTROL_CLEAR_SHIFT 31U
#define CMDSEQ_STATUS ((uint32_t)(0x598))
#define CMDSEQ_STATUS_OFFSET ((uint32_t)(0x198))
#define CMDSEQ_STATUS_RESET_VALUE 0x41000080U
#define CMDSEQ_STATUS_RESET_MASK 0xFFFFFFFFU
#define CMDSEQ_STATUS_FIFOSPACE_MASK 0x1FFFFU
#define CMDSEQ_STATUS_IDLE_MASK 0x40000000U
#endif
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <video/dpu.h>
#include <video/imx8-prefetch.h>
#include "dpu-blit.h"
#include "dpu-blit-registers.h"
#include "dpu-prv.h"
static inline u32 dpu_be_read(struct dpu_bliteng *dpu_be, unsigned int offset)
{
return readl(dpu_be->base + offset);
}
static inline void dpu_be_write(struct dpu_bliteng *dpu_be, u32 value,
unsigned int offset)
{
writel(value, dpu_be->base + offset);
}
static void dpu_cs_wait_fifo_space(struct dpu_bliteng *dpu_be)
{
while ((dpu_be_read(dpu_be, CMDSEQ_STATUS) &
CMDSEQ_STATUS_FIFOSPACE_MASK) < CMDSEQ_FIFO_SPACE_THRESHOLD)
usleep_range(1000, 2000);
}
static void dpu_cs_wait_idle(struct dpu_bliteng *dpu_be)
{
while ((dpu_be_read(dpu_be, CMDSEQ_STATUS) &
CMDSEQ_STATUS_IDLE_MASK) == 0x0)
mdelay(1);
}
static int dpu_cs_alloc_command_buffer(struct dpu_bliteng *dpu_be)
{
/* command buffer need 32 bit address */
dpu_be->buffer_addr_virt =
alloc_pages_exact(COMMAND_BUFFER_SIZE,
GFP_KERNEL | GFP_DMA | GFP_DMA32 | __GFP_ZERO);
if (!dpu_be->buffer_addr_virt) {
dev_err(dpu_be->dev, "memory alloc failed for dpu command buffer\n");
return -ENOMEM;
}
dpu_be->buffer_addr_phy =
(u32)virt_to_phys(dpu_be->buffer_addr_virt);
return 0;
}
static void dpu_cs_static_setup(struct dpu_bliteng *dpu_be)
{
dpu_cs_wait_idle(dpu_be);
/* LockUnlock and LockUnlockHIF */
dpu_be_write(dpu_be, CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNLOCK_KEY,
CMDSEQ_LOCKUNLOCKHIF);
dpu_be_write(dpu_be, CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY,
CMDSEQ_LOCKUNLOCK);
/* Control */
dpu_be_write(dpu_be, 1 << CMDSEQ_CONTROL_CLEAR_SHIFT,
CMDSEQ_CONTROL);
/* BufferAddress and BufferSize */
dpu_be_write(dpu_be, dpu_be->buffer_addr_phy, CMDSEQ_BUFFERADDRESS);
dpu_be_write(dpu_be, COMMAND_BUFFER_SIZE / WORD_SIZE,
CMDSEQ_BUFFERSIZE);
}
static struct dprc *
dpu_be_dprc_get(struct dpu_soc *dpu, int dprc_id)
{
struct dprc *dprc;
dprc = dprc_lookup_by_phandle(dpu->dev,
"fsl,dpr-channels",
dprc_id);
return dprc;
}
void dpu_be_configure_prefetch(struct dpu_bliteng *dpu_be,
u32 width, u32 height,
u32 x_offset, u32 y_offset,
u32 stride, u32 format, u64 modifier,
u64 baddr, u64 uv_addr)
{
static bool start = true;
static bool need_handle_start;
struct dprc *dprc;
/* Enable DPR, dprc1 is connected to plane0 */
dprc = dpu_be->dprc[1];
if (baddr == 0x0) {
dprc_disable(dprc);
start = true;
return;
}
dpu_be_wait(dpu_be);
if (need_handle_start) {
dprc_irq_handle(dprc);
need_handle_start = false;
}
dprc_configure(dprc, 0,
width, height,
x_offset, y_offset,
stride, format, modifier,
baddr, uv_addr,
start, start);
if (start)
dprc_enable(dprc);
dprc_reg_update(dprc);
if (start) {
dprc_enable_ctrl_done_irq(dprc);
need_handle_start = true;
}
start = false;
}
EXPORT_SYMBOL(dpu_be_configure_prefetch);
int dpu_bliteng_get_empty_instance(struct dpu_bliteng **dpu_be,
struct device *dev)
{
if (!dpu_be || !dev)
return -EINVAL;
*dpu_be = devm_kzalloc(dev, sizeof(struct dpu_bliteng), GFP_KERNEL);
if (!(*dpu_be))
return -ENOMEM;
return 0;
}
EXPORT_SYMBOL(dpu_bliteng_get_empty_instance);
u32 *dpu_bliteng_get_cmd_list(struct dpu_bliteng *dpu_be)
{
return dpu_be->cmd_list;
}
EXPORT_SYMBOL(dpu_bliteng_get_cmd_list);
s32 dpu_bliteng_get_id(struct dpu_bliteng *dpu_be)
{
return dpu_be->id;
}
EXPORT_SYMBOL(dpu_bliteng_get_id);
void dpu_bliteng_set_id(struct dpu_bliteng *dpu_be, int id)
{
dpu_be->id = id;
}
EXPORT_SYMBOL(dpu_bliteng_set_id);
void dpu_bliteng_set_dev(struct dpu_bliteng *dpu_be, struct device *dev)
{
dpu_be->dev = dev;
}
EXPORT_SYMBOL(dpu_bliteng_set_dev);
int dpu_be_get(struct dpu_bliteng *dpu_be)
{
mutex_lock(&dpu_be->mutex);
if (dpu_be->inuse) {
mutex_unlock(&dpu_be->mutex);
return -EBUSY;
}
dpu_be->inuse = true;
mutex_unlock(&dpu_be->mutex);
return 0;
}
EXPORT_SYMBOL(dpu_be_get);
void dpu_be_put(struct dpu_bliteng *dpu_be)
{
mutex_lock(&dpu_be->mutex);
dpu_be->inuse = false;
mutex_unlock(&dpu_be->mutex);
}
EXPORT_SYMBOL(dpu_be_put);
int dpu_be_blit(struct dpu_bliteng *dpu_be,
u32 *cmdlist, u32 cmdnum)
{
int i;
if (cmdnum > CMDSEQ_FIFO_SPACE_THRESHOLD) {
dev_err(dpu_be->dev, "dpu blit cmdnum[%d] should be less than %d !\n",
cmdnum, CMDSEQ_FIFO_SPACE_THRESHOLD);
return -EINVAL;
}
dpu_cs_wait_fifo_space(dpu_be);
for (i = 0; i < cmdnum; i++)
dpu_be_write(dpu_be, cmdlist[i], CMDSEQ_HIF);
return 0;
}
EXPORT_SYMBOL(dpu_be_blit);
#define STORE9_SEQCOMPLETE_IRQ 2U
#define STORE9_SEQCOMPLETE_IRQ_MASK (1U<<STORE9_SEQCOMPLETE_IRQ)
void dpu_be_wait(struct dpu_bliteng *dpu_be)
{
dpu_be_write(dpu_be, 0x10, PIXENGCFG_STORE9_TRIGGER);
while ((dpu_be_read(dpu_be, COMCTRL_INTERRUPTSTATUS0) &
STORE9_SEQCOMPLETE_IRQ_MASK) == 0)
usleep_range(1000, 2000);
dpu_be_write(dpu_be, STORE9_SEQCOMPLETE_IRQ_MASK,
COMCTRL_INTERRUPTCLEAR0);
}
EXPORT_SYMBOL(dpu_be_wait);
static void dpu_be_init_units(struct dpu_bliteng *dpu_be)
{
u32 staticcontrol;
u32 pixengcfg_unit_static, pixengcfg_unit_dynamic;
staticcontrol =
1 << FETCHDECODE9_STATICCONTROL_SHDEN_SHIFT |
0 << FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT |
FETCHDECODE9_STATICCONTROL_RESET_VALUE;
dpu_be_write(dpu_be, staticcontrol, FETCHDECODE9_STATICCONTROL);
staticcontrol =
1 << FETCHWARP9_STATICCONTROL_SHDEN_SHIFT |
0 << FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT |
FETCHWARP9_STATICCONTROL_RESET_VALUE;
dpu_be_write(dpu_be, staticcontrol, FETCHWARP9_STATICCONTROL);
staticcontrol =
1 << FETCHECO9_STATICCONTROL_SHDEN_SHIFT |
0 << FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT |
FETCHECO9_STATICCONTROL_RESET_VALUE;
dpu_be_write(dpu_be, staticcontrol, FETCHECO9_STATICCONTROL);
staticcontrol =
1 << HSCALER9_STATICCONTROL_SHDEN_SHIFT |
HSCALER9_STATICCONTROL_RESET_VALUE;
dpu_be_write(dpu_be, staticcontrol, HSCALER9_STATICCONTROL);
staticcontrol =
1 << VSCALER9_STATICCONTROL_SHDEN_SHIFT |
VSCALER9_STATICCONTROL_RESET_VALUE;
dpu_be_write(dpu_be, staticcontrol, VSCALER9_STATICCONTROL);
staticcontrol =
1 << ROP9_STATICCONTROL_SHDEN_SHIFT |
ROP9_STATICCONTROL_RESET_VALUE;
dpu_be_write(dpu_be, staticcontrol, ROP9_STATICCONTROL);
staticcontrol =
1 << MATRIX9_STATICCONTROL_SHDEN_SHIFT |
MATRIX9_STATICCONTROL_RESET_VALUE;
dpu_be_write(dpu_be, staticcontrol, MATRIX9_STATICCONTROL);
staticcontrol =
1 << BLITBLEND9_STATICCONTROL_SHDEN_SHIFT |
BLITBLEND9_STATICCONTROL_RESET_VALUE;
dpu_be_write(dpu_be, staticcontrol, BLITBLEND9_STATICCONTROL);
staticcontrol =
1 << STORE9_STATICCONTROL_SHDEN_SHIFT |