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Librem5
linux-emcraft
Commits
6595aea7
Commit
6595aea7
authored
Apr 17, 2019
by
Angus Ainslie (Purism)
Browse files
arm64: dts: fsl: librem5: Drop imx8_som node
We don't need the imx8_som node drop it. Signed-off-by:
Angus Ainslie (Purism)
<
angus@akkea.ca
>
parent
12f3cf5d
Pipeline
#6303
passed with stage
in 39 minutes and 8 seconds
Changes
1
Pipelines
1
Hide whitespace changes
Inline
Side-by-side
arch/arm64/boot/dts/freescale/librem5-evk.dtsi
View file @
6595aea7
...
...
@@ -209,390 +209,387 @@
};
&
iomuxc
{
imx8m
-
som
{
pinctrl_nc
:
ncgrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK
0x00
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL
0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA
0x4000007f
>;
};
pinctrl_up
:
upgrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2
0x00
>;
};
pinctrl_nc
:
ncgrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK
0x00
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL
0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA
0x4000007f
>;
};
pinctrl_csi1
:
csi1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6
0x11
/*
CSI_nRST
*/
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7
0x19
/*
CSI_PWDN
*/
MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1
0x19
/*
CLK01
*/
>;
};
pinctrl_up
:
upgrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2
0x00
>;
};
pinctrl_pwr_en
:
pwr_engrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8
0x06
>;
};
pinctrl_csi1
:
csi1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6
0x11
/*
CSI_nRST
*/
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7
0x19
/*
CSI_PWDN
*/
MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1
0x19
/*
CLK01
*/
>;
};
pinctrl_wwan
:
wwan_grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4
0x09
/*
nWWAN_DISABLE
*/
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8
0x80
/*
nWoWWAN
*/
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9
0x19
/*
WWAN_RESET
*/
>;
};
pinctrl_pwr_en
:
pwr_engrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8
0x06
>;
};
pinctrl_dsi
:
dsigrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13
0x16
>;
};
pinctrl_wwan
:
wwan_grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4
0x09
/*
nWWAN_DISABLE
*/
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8
0x80
/*
nWoWWAN
*/
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9
0x19
/*
WWAN_RESET
*/
>;
};
pinctrl_fec1
:
fec1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC
0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO
0x3
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9
0x19
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2
0x1f
>;
};
pinctrl_dsi
:
dsigrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13
0x16
>;
};
pinctrl_hdmi
:
hdmigrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2
0x16
>;
};
pinctrl_fec1
:
fec1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC
0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO
0x3
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9
0x19
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2
0x1f
>;
};
pinctrl_i2c1
:
i2c1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL
0x4000001f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA
0x4000001f
>;
};
pinctrl_hdmi
:
hdmigrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2
0x16
>;
};
pinctrl_i2c
2
:
i2c
2
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_I2C
2
_SCL_I2C
2
_SCL
0x4000001f
MX8MQ_IOMUXC_I2C
2
_SDA_I2C
2
_SDA
0x4000001f
>;
};
pinctrl_i2c
1
:
i2c
1
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_I2C
1
_SCL_I2C
1
_SCL
0x4000001f
MX8MQ_IOMUXC_I2C
1
_SDA_I2C
1
_SDA
0x4000001f
>;
};
pinctrl_i2c
3
:
i2c
3
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_I2C
3
_SCL_I2C
3
_SCL
0x4000001f
MX8MQ_IOMUXC_I2C
3
_SDA_I2C
3
_SDA
0x4000001f
>;
};
pinctrl_i2c
2
:
i2c
2
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_I2C
2
_SCL_I2C
2
_SCL
0x4000001f
MX8MQ_IOMUXC_I2C
2
_SDA_I2C
2
_SDA
0x4000001f
>;
};
pinctrl_pcie0
:
pcie0grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15
0x16
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11
0x16
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10
0x16
>;
};
pinctrl_i2c3
:
i2c3grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL
0x4000001f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA
0x4000001f
>;
};
pinctrl_pcie
1
:
pcie
1
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_
WP
_B_GPIO3_IO1
8
0x16
MX8MQ_IOMUXC_NAND_
CLE
_GPIO3_IO
5
0x16
MX8MQ_IOMUXC_NAND_
WE_B
_GPIO3_IO1
7
0x16
>;
};
pinctrl_pcie
0
:
pcie
0
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_
RE
_B_GPIO3_IO1
5
0x16
MX8MQ_IOMUXC_NAND_
DATA05
_GPIO3_IO
11
0x16
MX8MQ_IOMUXC_NAND_
DATA04
_GPIO3_IO1
0
0x16
>;
};
pinctrl_pcie1
:
pcie1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18
0x16
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5
0x16
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17
0x16
>;
};
pinctrl_typec
:
typecgrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12
0x16
MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1
0x80
>;
};
pinctrl_
uart1
:
uart1
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_
UART1_RXD_UART1_DCE_RX
0x
49
MX8MQ_IOMUXC_
UART1_TXD_UART1_DCE_TX
0x
49
>;
};
pinctrl_
typec
:
typec
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_
NAND_DATA06_GPIO3_IO12
0x
16
MX8MQ_IOMUXC_
NAND_CE0_B_GPIO3_IO1
0x
80
>;
};
pinctrl_uart2
:
uart2grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX
0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX
0x49
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B
0x49
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B
0x49
>;
};
pinctrl_uart1
:
uart1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX
0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX
0x49
>;
};
pinctrl_uart3
:
uart3grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX
0x49
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX
0x49
>;
};
pinctrl_uart2
:
uart2grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX
0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX
0x49
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B
0x49
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B
0x49
>;
};
pinctrl_uart4
:
uart4grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX
0x49
MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX
0x49
MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B
0x49
MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B
0x49
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
0x49
>;
};
pinctrl_uart3
:
uart3grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX
0x49
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX
0x49
>;
};
pinctrl_bt
:
btgrp
{
fsl
,
pins
=
<
/*
BT_REG_ON
*/
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11
0x16
/*
nBT_DISABLE
*/
MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7
0x10
/*
BT_HOST_WAKE
*/
>;
};
pinctrl_uart4
:
uart4grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX
0x49
MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX
0x49
MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B
0x49
MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B
0x49
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
0x49
>;
};
pinctrl_modem_reset
:
modem_reset
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9
0x19
/*
WWAN_RESET
*/
pinctrl_bt
:
btgrp
{
fsl
,
pins
=
<
/*
BT_REG_ON
*/
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11
0x16
/*
nBT_DISABLE
*/
MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7
0x10
/*
BT_HOST_WAKE
*/
>;
};
};
pinctrl_usdhc1
:
usdhc1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
0xc1
>;
};
pinctrl_modem_reset
:
modem_reset
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9
0x19
/*
WWAN_RESET
*/
>;
};
pinctrl_usdhc1
_100mhz
:
usdhc1grp
100mhz
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
0x8
d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
0xc
d
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
0xc
d
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
0xc
d
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
0xc
d
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
0xc
d
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
0xc
d
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
0xc
d
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
0xc
d
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
0xc
d
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
0x8
d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
0xc1
>;
};
pinctrl_usdhc1
:
usdhc1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
0x8
3
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
0xc
3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
0xc
3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
0xc
3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
0xc
3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
0xc
3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
0xc
3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
0xc
3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
0xc
3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
0xc
3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
0x8
3
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
0xc1
>;
};
pinctrl_usdhc1_
2
00mhz
:
usdhc1grp
2
00mhz
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
0x
9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
0xd
f
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
0xd
f
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
0xd
f
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
0xd
f
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
0xd
f
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
0xd
f
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
0xd
f
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
0xd
f
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
0xd
f
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
0x
9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
0xc1
>;
};
pinctrl_usdhc1_
1
00mhz
:
usdhc1grp
1
00mhz
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
0x
8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
0x
c
d
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
0x
c
d
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
0x
c
d
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
0x
c
d
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
0x
c
d
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
0x
c
d
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
0x
c
d
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
0x
c
d
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
0x
c
d
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
0x
8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
0xc1
>;
};
pinctrl_usdhc2_gpio
:
usdhc2grpgpio
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19
0x41
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20
0x80
/*
WIFI_WAKE
*/
>;
};
pinctrl_usdhc1_200mhz
:
usdhc1grp200mhz
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
0xc1
>;
};
pinctrl_usdhc2
:
usdhc2grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK
0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
0xc3
>;
};
pinctrl_usdhc2_gpio
:
usdhc2grpgpio
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19
0x41
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20
0x80
/*
WIFI_WAKE
*/
>;
};
pinctrl_usdhc2
_100mhz
:
usdhc2grp
100mhz
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK
0x8
d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
0xc
d
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
0xc
d
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
0xc
d
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
0xc
d
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
0xc
d
>;
};
pinctrl_usdhc2
:
usdhc2grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK
0x8
3
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
0xc
3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
0xc
3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
0xc
3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
0xc
3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
0xc
3
>;
};
pinctrl_usdhc2_
2
00mhz
:
usdhc2grp
2
00mhz
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK
0x
9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
0xc
f
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
0xc
f
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
0xc
f
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
0xc
f
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
0xc
f
>;
};
pinctrl_usdhc2_
1
00mhz
:
usdhc2grp
1
00mhz
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK
0x
8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
0xc
d
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
0xc
d
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
0xc
d
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
0xc
d
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
0xc
d
>;
};
pinctrl_sai2
:
sai2grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC
0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK
0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0
0xd6
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0
0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK
0xd6
>;
};
pinctrl_usdhc2_200mhz
:
usdhc2grp200mhz
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK
0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
0xcf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
0xcf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
0xcf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
0xcf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
0xcf
>;
};
pinctrl_sai5
:
sai5grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0
0xd6
MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC
0xd6
MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK
0xd6
MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0
0xd6
>;
};
pinctrl_sai2
:
sai2grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC
0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK
0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0
0xd6
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0
0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK
0xd6
>;
};
pinctrl_sai
6
:
sai
6
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI
1
_RXD
5
_SAI
6_R
X_DATA0
0xd6
MX8MQ_IOMUXC_SAI
1
_RXD
6
_SAI
6_R
X_SYNC
0xd6
MX8MQ_IOMUXC_SAI
1_T
XD
4
_SAI
6_R
X_BCLK
0xd6
MX8MQ_IOMUXC_SAI
1_T
XD
5
_SAI
6_T
X_DATA0
0xd6
>;
};
pinctrl_sai
5
:
sai
5
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI
5
_RXD
3
_SAI
5_T
X_DATA0
0xd6
MX8MQ_IOMUXC_SAI
5
_RXD
1
_SAI
5_T
X_SYNC
0xd6
MX8MQ_IOMUXC_SAI
5_R
XD
2
_SAI
5_T
X_BCLK
0xd6
MX8MQ_IOMUXC_SAI
5_R
XD
0
_SAI
5_R
X_DATA0
0xd6
>;
};
pinctrl_spdif1
:
spdif1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT
0xd6
MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN
0xd6
>;
};
pinctrl_sai6
:
sai6grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0
0xd6
MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC
0xd6
MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK
0xd6
MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0
0xd6
>;
};
pinctrl_wdog
:
wdoggrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
0xc6
>;
};
pinctrl_spdif1
:
spdif1grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT
0xd6
MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN
0xd6
>;
};
pinctrl_
pwm1
:
pwm1
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_GPIO1_IO0
1_PWM1_OUT
0x6
/*
DSI_BL_PWM
*/
>;
};
pinctrl_
wdog
:
wdoggrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_GPIO1_IO0
2_WDOG1_WDOG_B
0xc6
>;
};
pinctrl_
micsel
:
micselgrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_
SPDIF_EXT_CLK_GPIO5_IO5
0x
c
6
/*
mic
sel
*/
>;
};
pinctrl_
pwm1
:
pwm1
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_
GPIO1_IO01_PWM1_OUT
0x6
/*
DSI_BL_PWM
*/
>;
};
pinctrl_
haptic
:
haptic
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SPDIF_
RX_PWM2_OUT
0xc6
/*
nHAPTIC
*/
>;
};
pinctrl_
micsel
:
micsel
grp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SPDIF_
EXT_CLK_GPIO5_IO5
0xc6
/*
mic
sel
*/
>;
};
pinctrl_
mute
:
mute
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SPDIF_
T
X_
GPIO5_IO3
0x
8
6
/*
MUTE
*/
>;
};
pinctrl_
haptic
:
hapticgrp
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_SPDIF_
R
X_
PWM2_OUT
0x
c
6
/*
nHAPTIC
*/
>;
};
pinctrl_
pwm4
:
pwm4
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_
I2C3_SCL_PWM4_OUT
0xc6
>;
};
pinctrl_
mute
:
mute
{
fsl
,
pins
=
<
MX8MQ_IOMUXC_
SPDIF_TX_GPIO5_IO3
0x86
/*
MUTE
*/
>;