Commit 89a71e79 authored by Angus Ainslie's avatar Angus Ainslie
Browse files

Merge branch 'imx8-4.18-fixes' into 'imx8-4.18-wip'

Imx8 4.18 fixes

See merge request !24
parents 25a8cc5f 6595aea7
Pipeline #6384 passed with stage
in 40 minutes and 23 seconds
......@@ -109,31 +109,6 @@
};
};
#if TODO
sound-hdmi {
compatible = "fsl,imx-audio-cdnhdmi";
model = "imx-audio-hdmi";
audio-cpu = <&sai4>;
protocol = <1>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
status = "disabled";
};
sound-hdmi-arc {
compatible = "fsl,imx-audio-spdif";
model = "imx-hdmi-arc";
spdif-controller = <&spdif2>;
spdif-in;
};
#endif
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
......@@ -234,390 +209,387 @@
};
&iomuxc {
imx8m-som {
pinctrl_nc: ncgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x00
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_up: upgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x00
>;
};
pinctrl_nc: ncgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x00
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_csi1: csi1grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x11 /* CSI_nRST */
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* CSI_PWDN */
MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x19 /* CLK01 */
>;
};
pinctrl_up: upgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x00
>;
};
pinctrl_pwr_en: pwr_engrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
>;
};
pinctrl_csi1: csi1grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x11 /* CSI_nRST */
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* CSI_PWDN */
MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x19 /* CLK01 */
>;
};
pinctrl_wwan: wwan_grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
>;
};
pinctrl_pwr_en: pwr_engrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
>;
};
pinctrl_dsi: dsigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x16
>;
};
pinctrl_wwan: wwan_grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
>;
};
pinctrl_dsi: dsigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x16
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x16
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x16
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000001f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000001f
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000001f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000001f
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x16
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x16
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
>;
};
pinctrl_bt: btgrp {
fsl,pins = <
/* BT_REG_ON */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */
MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
>;
};
pinctrl_modem_reset: modem_reset {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
pinctrl_bt: btgrp {
fsl,pins = <
/* BT_REG_ON */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */
MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */
>;
};
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_modem_reset: modem_reset {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
>;
};
pinctrl_sai6: sai6grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_sai6: sai6grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_pwm1: pwm1 {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_micsel: micselgrp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6 /* mic sel */
>;
};
pinctrl_pwm1: pwm1 {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */
>;
};
pinctrl_haptic: hapticgrp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0xc6 /* nHAPTIC */
>;
};