Commit 616433a7 authored by Bob Ham's avatar Bob Ham

Merge branch 'imx8-4.18-drop-dpu' into 'imx8-4.18-wip'

Drop DPU related bits

See merge request !26
parents 6155516c 087e3ad5
Pipeline #8436 passed with stage
in 47 minutes and 30 seconds
config IMX8_PRG
tristate
default y if IMX_DPU_CORE=y
default m if IMX_DPU_CORE=m
config IMX8_DPRC
tristate
default y if IMX_DPU_CORE=y
default m if IMX_DPU_CORE=m
source drivers/gpu/imx/dpu/Kconfig
source drivers/gpu/imx/dpu-blit/Kconfig
source drivers/gpu/imx/dcss/Kconfig
obj-$(CONFIG_IMX8_PRG) += imx8_prg.o
obj-$(CONFIG_IMX8_DPRC) += imx8_dprc.o
obj-$(CONFIG_IMX_DPU_CORE) += dpu/
obj-$(CONFIG_IMX_DPU_BLIT) += dpu-blit/
obj-$(CONFIG_IMX_DCSS_CORE) += dcss/
config IMX_DPU_BLIT
tristate
depends on IMX_DPU_CORE
default y if IMX_DPU_CORE=y
default m if IMX_DPU_CORE=m
ccflags-y += -Idrivers/gpu/imx/dpu
imx-dpu-blit-objs := dpu-blit.o
obj-$(CONFIG_IMX_DPU_BLIT) += imx-dpu-blit.o
This diff is collapsed.
This diff is collapsed.
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef __DPU_BLIT_H__
#define __DPU_BLIT_H__
#define COMMAND_BUFFER_SIZE 65536 /* up to 64k bytes */
#define CMDSEQ_FIFO_SPACE_THRESHOLD 192
#define WORD_SIZE 4
struct dpu_bliteng {
struct device *dev;
void __iomem *base;
s32 id;
struct mutex mutex;
bool inuse;
s32 irq_store9_shdload;
s32 irq_store9_framecomplete;
s32 irq_store9_seqcomplete;
void *buffer_addr_virt;
u32 buffer_addr_phy;
u32 *cmd_list;
struct dpu_soc *dpu;
struct dprc *dprc[2];
};
#endif
config IMX_DPU_CORE
tristate "i.MX DPU core support"
depends on ARCH_FSL_IMX8QM || ARCH_FSL_IMX8QXP
depends on RESET_CONTROLLER
select GENERIC_IRQ_CHIP
select IMX8_PRG
select IMX8_DPRC
help
Choose this if you have a Freescale i.MX8QM or i.MX8QXP system and
want to use the Display Processing Unit. This option only enables
DPU base support.
obj-$(CONFIG_IMX_DPU_CORE) += imx-dpu-core.o
imx-dpu-core-objs := dpu-common.o dpu-constframe.o dpu-disengcfg.o \
dpu-extdst.o dpu-fetchdecode.o dpu-fetcheco.o \
dpu-framegen.o dpu-fetchlayer.o dpu-hscaler.o \
dpu-layerblend.o dpu-tcon.o dpu-vscaler.o
This diff is collapsed.
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <video/dpu.h>
#include "dpu-prv.h"
static unsigned int safety_stream_cf_color = 0x0;
module_param(safety_stream_cf_color, uint, 0444);
MODULE_PARM_DESC(safety_stream_cf_color,
"Safety stream constframe color in hex(0xRRGGBBAA) [default=0x00000000]");
#define FRAMEDIMENSIONS 0xC
#define WIDTH(w) (((w) - 1) & 0x3FFF)
#define HEIGHT(h) ((((h) - 1) & 0x3FFF) << 16)
#define CONSTANTCOLOR 0x10
#define RED(r) (((r) & 0xFF) << 24)
#define GREEN(g) (((g) & 0xFF) << 16)
#define BLUE(b) (((b) & 0xFF) << 8)
#define ALPHA(a) ((a) & 0xFF)
#define CONTROLTRIGGER 0x14
#define START 0x18
#define STATUS 0x1C
static const shadow_load_req_t cf_shdlreqs[] = {
SHLDREQID_CONSTFRAME0, SHLDREQID_CONSTFRAME1,
SHLDREQID_CONSTFRAME4, SHLDREQID_CONSTFRAME5,
};
struct dpu_constframe {
void __iomem *pec_base;
void __iomem *base;
struct mutex mutex;
int id;
bool inuse;
struct dpu_soc *dpu;
shadow_load_req_t shdlreq;
};
static inline void dpu_cf_write(struct dpu_constframe *cf, u32 value,
unsigned int offset)
{
writel(value, cf->base + offset);
}
void constframe_shden(struct dpu_constframe *cf, bool enable)
{
u32 val;
val = enable ? SHDEN : 0;
mutex_lock(&cf->mutex);
dpu_cf_write(cf, val, STATICCONTROL);
mutex_unlock(&cf->mutex);
}
EXPORT_SYMBOL_GPL(constframe_shden);
void constframe_framedimensions(struct dpu_constframe *cf, unsigned int w,
unsigned int h)
{
u32 val;
val = WIDTH(w) | HEIGHT(h);
mutex_lock(&cf->mutex);
dpu_cf_write(cf, val, FRAMEDIMENSIONS);
mutex_unlock(&cf->mutex);
}
EXPORT_SYMBOL_GPL(constframe_framedimensions);
void constframe_constantcolor(struct dpu_constframe *cf, unsigned int r,
unsigned int g, unsigned int b, unsigned int a)
{
u32 val;
val = RED(r) | GREEN(g) | BLUE(b) | ALPHA(a);
mutex_lock(&cf->mutex);
dpu_cf_write(cf, val, CONSTANTCOLOR);
mutex_unlock(&cf->mutex);
}
EXPORT_SYMBOL_GPL(constframe_constantcolor);
void constframe_controltrigger(struct dpu_constframe *cf, bool trigger)
{
u32 val;
val = trigger ? SHDTOKGEN : 0;
mutex_lock(&cf->mutex);
dpu_cf_write(cf, val, CONTROLTRIGGER);
mutex_unlock(&cf->mutex);
}
EXPORT_SYMBOL_GPL(constframe_controltrigger);
shadow_load_req_t constframe_to_shdldreq_t(struct dpu_constframe *cf)
{
shadow_load_req_t t = 0;
switch (cf->id) {
case 0:
t = SHLDREQID_CONSTFRAME0;
break;
case 1:
t = SHLDREQID_CONSTFRAME1;
break;
case 4:
t = SHLDREQID_CONSTFRAME4;
break;
case 5:
t = SHLDREQID_CONSTFRAME5;
break;
}
return t;
}
EXPORT_SYMBOL_GPL(constframe_to_shdldreq_t);
struct dpu_constframe *dpu_cf_get(struct dpu_soc *dpu, int id)
{
struct dpu_constframe *cf;
int i;
for (i = 0; i < ARRAY_SIZE(cf_ids); i++)
if (cf_ids[i] == id)
break;
if (i == ARRAY_SIZE(cf_ids))
return ERR_PTR(-EINVAL);
cf = dpu->cf_priv[i];
mutex_lock(&cf->mutex);
if (cf->inuse) {
cf = ERR_PTR(-EBUSY);
goto out;
}
cf->inuse = true;
out:
mutex_unlock(&cf->mutex);
return cf;
}
EXPORT_SYMBOL_GPL(dpu_cf_get);
void dpu_cf_put(struct dpu_constframe *cf)
{
mutex_lock(&cf->mutex);
cf->inuse = false;
mutex_unlock(&cf->mutex);
}
EXPORT_SYMBOL_GPL(dpu_cf_put);
void _dpu_cf_init(struct dpu_soc *dpu, unsigned int id)
{
struct dpu_constframe *cf;
int i;
for (i = 0; i < ARRAY_SIZE(cf_ids); i++)
if (cf_ids[i] == id)
break;
if (WARN_ON(i == ARRAY_SIZE(cf_ids)))
return;
cf = dpu->cf_priv[i];
constframe_shden(cf, true);
if (id == 4 || id == 5) {
mutex_lock(&cf->mutex);
dpu_cf_write(cf, safety_stream_cf_color, CONSTANTCOLOR);
mutex_unlock(&cf->mutex);
}
}
int dpu_cf_init(struct dpu_soc *dpu, unsigned int id,
unsigned long pec_base, unsigned long base)
{
struct dpu_constframe *cf;
int i;
cf = devm_kzalloc(dpu->dev, sizeof(*cf), GFP_KERNEL);
if (!cf)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(cf_ids); i++)
if (cf_ids[i] == id)
break;
dpu->cf_priv[i] = cf;
cf->pec_base = devm_ioremap(dpu->dev, pec_base, SZ_16);
if (!cf->pec_base)
return -ENOMEM;
cf->base = devm_ioremap(dpu->dev, base, SZ_32);
if (!cf->base)
return -ENOMEM;
cf->dpu = dpu;
cf->id = id;
cf->shdlreq = cf_shdlreqs[i];
mutex_init(&cf->mutex);
_dpu_cf_init(dpu, id);
return 0;
}
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <drm/drm_mode.h>
#include <linux/io.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include "dpu-prv.h"
#define CLOCKCTRL 0x8
typedef enum {
DSPCLKDIVIDE__DIV1, /* Ext disp clk signal has pix clk freq. */
DSPCLKDIVIDE__DIV2, /* Ext disp clk signal has 2x the pix clk freq. */
} clkdivide_t;
#define POLARITYCTRL 0xC
#define POLHS_HIGH BIT(0)
#define POLVS_HIGH BIT(1)
#define POLEN_HIGH BIT(2)
#define PIXINV_INV BIT(3)
#define SRCSELECT 0x10
struct dpu_disengcfg {
void __iomem *base;
struct mutex mutex;
int id;
bool inuse;
struct dpu_soc *dpu;
};
static inline u32 dpu_dec_read(struct dpu_disengcfg *dec, unsigned int offset)
{
return readl(dec->base + offset);
}
static inline void dpu_dec_write(struct dpu_disengcfg *dec, u32 value,
unsigned int offset)
{
writel(value, dec->base + offset);
}
void disengcfg_polarity_ctrl(struct dpu_disengcfg *dec, unsigned int flags)
{
const struct dpu_devtype *devtype = dec->dpu->devtype;
u32 val;
mutex_lock(&dec->mutex);
val = dpu_dec_read(dec, POLARITYCTRL);
if (devtype->pixel_link_nhvsync) {
val &= ~POLHS_HIGH;
val &= ~POLVS_HIGH;
} else {
if (flags & DRM_MODE_FLAG_PHSYNC)
val |= POLHS_HIGH;
if (flags & DRM_MODE_FLAG_NHSYNC)
val &= ~POLHS_HIGH;
if (flags & DRM_MODE_FLAG_PVSYNC)
val |= POLVS_HIGH;
if (flags & DRM_MODE_FLAG_NVSYNC)
val &= ~POLVS_HIGH;
}
dpu_dec_write(dec, val, POLARITYCTRL);
mutex_unlock(&dec->mutex);
}
EXPORT_SYMBOL_GPL(disengcfg_polarity_ctrl);
struct dpu_disengcfg *dpu_dec_get(struct dpu_soc *dpu, int id)
{
struct dpu_disengcfg *dec;
int i;
for (i = 0; i < ARRAY_SIZE(dec_ids); i++)
if (dec_ids[i] == id)
break;
if (i == ARRAY_SIZE(dec_ids))
return ERR_PTR(-EINVAL);
dec = dpu->dec_priv[i];
mutex_lock(&dec->mutex);
if (dec->inuse) {
dec = ERR_PTR(-EBUSY);
goto out;
}
dec->inuse = true;
out:
mutex_unlock(&dec->mutex);
return dec;
}
EXPORT_SYMBOL_GPL(dpu_dec_get);
void dpu_dec_put(struct dpu_disengcfg *dec)
{
mutex_lock(&dec->mutex);
dec->inuse = false;
mutex_unlock(&dec->mutex);
}
EXPORT_SYMBOL_GPL(dpu_dec_put);
void _dpu_dec_init(struct dpu_soc *dpu, unsigned int id)
{
}
int dpu_dec_init(struct dpu_soc *dpu, unsigned int id,
unsigned long unused, unsigned long base)
{
struct dpu_disengcfg *dec;
dec = devm_kzalloc(dpu->dev, sizeof(*dec), GFP_KERNEL);
if (!dec)
return -ENOMEM;
dpu->dec_priv[id] = dec;
dec->base = devm_ioremap(dpu->dev, base, SZ_16);
if (!dec->base)
return -ENOMEM;
dec->dpu = dpu;
dec->id = id;
mutex_init(&dec->mutex);
return 0;
}
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment