Commit baab9c10 authored by Guido Günther's avatar Guido Günther

Merge branch 'f/4.18/drm' into imx8-4.18-wip

parents b0600f7a a1dd529d
Pipeline #3420 passed with stage
in 34 minutes and 39 seconds
......@@ -336,6 +336,7 @@ static void nwl_dsi_config_host(struct nwl_mipi_dsi *dsi)
if (dsi->lanes < 1 || dsi->lanes > 4)
return;
DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d", dsi->lanes);
nwl_dsi_write(dsi, CFG_NUM_LANES, dsi->lanes - 1);
if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
......@@ -372,6 +373,15 @@ static void nwl_dsi_config_dpi(struct nwl_mipi_dsi *dsi)
u32 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
bool burst_mode;
DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d", vm->hfront_porch);
DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d", vm->hback_porch);
DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d", vm->hsync_len);
DRM_DEV_DEBUG_DRIVER(dsi->dev, "hactive = %d", vm->hactive);
DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d", vm->vfront_porch);
DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d", vm->vback_porch);
DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d", vm->vsync_len);
DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d", vm->vactive);
nwl_dsi_write(dsi, INTERFACE_COLOR_CODING, DPI_24_BIT);
nwl_dsi_write(dsi, PIXEL_FORMAT, color_format);
/*TODO: need to make polarity configurable */
......@@ -811,7 +821,7 @@ static void nwl_dsi_begin_transmission(struct nwl_mipi_dsi *dsi)
* header structure is:
* header[0] = Virtual Channel + Data Type
* header[1] = Word Count LSB (LP) or first param (SP)
* header[2] = Word Count MSB (LP) or first param (SP)
* header[2] = Word Count MSB (LP) or second param (SP)
*/
word_count = pkt->header[1] | (pkt->header[2] << 8);
hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM)?0:1;
......
......@@ -53,10 +53,8 @@ static const struct drm_display_mode default_mode = {
.vsync_start = 1440 + 20 /* front porch */,
.vsync_end = 1440 + 20 + 4 /* sync_len */,
.vtotal = 1440 + 20 + 4 + 12 /* back porch */,
.vrefresh = 60, /* confirmed from qualcom XML */
/* htotal * vtotal * vrefresh / 1000 */
/* actually 71638 but vendor suggets 75 Mhz */
.clock = 75000, /* kHz */
.vrefresh = 60,
.clock = 75276, /* kHz */
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
.width_mm = 65,
.height_mm = 130,
......@@ -68,119 +66,94 @@ static inline struct jh057n *panel_to_jh057n(struct drm_panel *panel)
return container_of(panel, struct jh057n, panel);
}
static void jh057n_dcs_write_buf(struct jh057n *ctx, const void *data,
size_t len)
static void jh057n_dsi_generic_write_buf(struct jh057n *ctx, const void *data,
size_t len)
{
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
if (mipi_dsi_generic_write(dsi, data, len) < 0)
DRM_DEV_ERROR(ctx->dev, "mipi dsi dcs write buffer failed\n");
DRM_DEV_ERROR(ctx->dev, "mipi dsi generic write buffer failed\n");
}
#define dcs_write_seq(ctx, seq...) \
({ \
static const u8 d[] = { seq }; \
jh057n_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
#define dsi_generic_write_seq(ctx, seq...) \
({ \
static const u8 d[] = { seq }; \
jh057n_dsi_generic_write_buf(ctx, d, ARRAY_SIZE(d)); \
})
static int jh057n_dcs_read_one(struct jh057n *ctx, u8 cmd, u8 *data)
{
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
u8 in[] = { cmd };
u8 out[1] = { 0 };
int ret;
ret = mipi_dsi_generic_read(dsi, in, ARRAY_SIZE(in), out, ARRAY_SIZE(out));
if (ret < 0) {
DRM_DEV_DEBUG_DRIVER(ctx->dev, "Couldn't read %d: %d", cmd, ret);
return ret;
}
if (ret == 0) {
DRM_DEV_DEBUG_DRIVER(ctx->dev, "Couldn't read %d, no data read", cmd);
return -EINVAL;
}
data[0] = out[0];
return ret;
}
static int jh057n_init_sequence(struct jh057n *ctx)
{
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
struct device *dev = ctx->dev;
int ret;
u8 out[1] = { 0 };
msleep(200);
/* Enable user command */
dcs_write_seq(ctx, ST7703_CMD_SETEXTC, /* 3 */
0xF1, 0x12, 0x83);
dsi_generic_write_seq(ctx, ST7703_CMD_SETEXTC, /* 3 */
0xF1, 0x12, 0x83);
/* 6 params in ST7703 docs */
dcs_write_seq(ctx, ST7703_CMD_SETMIPI, /* 27 */
0x33, 0x81, 0x05, 0xF9, 0x0E, 0x0E, 0x20, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25,
0x00, 0x91, 0x0A, 0x00, 0x00, 0x02, 0x4F, 0x11,
0x00, 0x00, 0x37);
dsi_generic_write_seq(ctx, ST7703_CMD_SETMIPI, /* 27 */
0x33, 0x81, 0x05, 0xF9, 0x0E, 0x0E, 0x20, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25,
0x00, 0x91, 0x0A, 0x00, 0x00, 0x02, 0x4F, 0x11,
0x00, 0x00, 0x37);
/* 6 params in ST7703 docs */
dcs_write_seq(ctx, ST7703_CMD_SETPOWER_EXT, /* 4 */
0x76, 0x22, 0x20, 0x03);
dsi_generic_write_seq(ctx, ST7703_CMD_SETPOWER_EXT, /* 4 */
0x76, 0x22, 0x20, 0x03);
/* 4 params in ST7703 docs */
dcs_write_seq(ctx, ST7703_CMD_SETRGBIF, /* 10 */
0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00,
0x00, 0x00);
dsi_generic_write_seq(ctx, ST7703_CMD_SETRGBIF, /* 10 */
0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00,
0x00, 0x00);
/* 8 params in ST7703 docs */
dcs_write_seq(ctx, ST7703_CMD_SETSCR, /* 9 */
0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
0x00);
dsi_generic_write_seq(ctx, ST7703_CMD_SETSCR, /* 9 */
0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
0x00);
/* -1.6V & + 1.9V */
dcs_write_seq(ctx, ST7703_CMD_SETVDC, 0x4E);
dsi_generic_write_seq(ctx, ST7703_CMD_SETVDC, 0x4E);
/* SS_PANEL, REV_PANEL, BGR_PANEL */
dcs_write_seq(ctx, ST7703_CMD_SETPANEL, 0x0B);
dsi_generic_write_seq(ctx, ST7703_CMD_SETPANEL, 0x0B);
/* 2 params in ST7703 docs */
dcs_write_seq(ctx, ST7703_CMD_SETCYC, 0x80);
dsi_generic_write_seq(ctx, ST7703_CMD_SETCYC, 0x80);
/* weird values, e.g. a 720 panel has BIT(1) 3rd param */
dcs_write_seq(ctx, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30);
dcs_write_seq(ctx, ST7703_CMD_SETEQ, /* 14 */
0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,
0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);
dcs_write_seq(ctx, ST7703_CMD_SETPOWER, /* 12 */
0x54, 0x00, 0x1E, 0x1E, 0x77, 0xF1, 0xFF, 0xFF,
0xCC, 0xCC, 0x77, 0x77);
dsi_generic_write_seq(ctx, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30);
dsi_generic_write_seq(ctx, ST7703_CMD_SETEQ, /* 14 */
0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,
0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);
dsi_generic_write_seq(ctx, ST7703_CMD_SETPOWER, /* 12 */
0x54, 0x00, 0x1E, 0x1E, 0x77, 0xF1, 0xFF, 0xFF,
0xCC, 0xCC, 0x77, 0x77);
/* setbgp is different from our first data set*/
dcs_write_seq(ctx, ST7703_CMD_SETBGP, 0x08, 0x08);
dsi_generic_write_seq(ctx, ST7703_CMD_SETBGP, 0x08, 0x08);
mdelay(100);
/* setvcom is different from our first data set*/
dcs_write_seq(ctx, ST7703_CMD_SETVCOM, 0x3F, 0x3F);
dsi_generic_write_seq(ctx, ST7703_CMD_SETVCOM, 0x3F, 0x3F);
/* undocumented */
dcs_write_seq(ctx, 0xBF, 0x02, 0x11, 0x00);
dcs_write_seq(ctx, ST7703_CMD_SETGIP1, /* 63 */
0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12,
0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88,
0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64,
0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
dsi_generic_write_seq(ctx, 0xBF, 0x02, 0x11, 0x00);
dsi_generic_write_seq(ctx, ST7703_CMD_SETGIP1, /* 63 */
0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12,
0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88,
0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64,
0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
/* 39 parameters accordin to ST7703 docs */
dcs_write_seq(ctx, ST7703_CMD_SETGIP2, /* 61 */
0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A,
0xA5, 0x00, 0x00, 0x00, 0x00);
dcs_write_seq(ctx, ST7703_CMD_SETGAMMA, /* 34 */
0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37,
0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11,
0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41,
0x37, 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10,
0x11, 0x18);
dsi_generic_write_seq(ctx, ST7703_CMD_SETGIP2, /* 61 */
0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A,
0xA5, 0x00, 0x00, 0x00, 0x00);
dsi_generic_write_seq(ctx, ST7703_CMD_SETGAMMA, /* 34 */
0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37,
0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11,
0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41,
0x37, 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10,
0x11, 0x18);
msleep(78); /* docs say nothing here */
......@@ -191,17 +164,6 @@ static int jh057n_init_sequence(struct jh057n *ctx)
}
msleep(150); /* docs say 120ms */
#if 0
/* This fails if we do more than the first "enter user mode" command and if fails
* always when we do *any* command and turn of the clock in nwl-dsi.c */
/* check panel */
if (jh057n_dcs_read_one(ctx, MIPI_DCS_GET_DIAGNOSTIC_RESULT, out) < 0)
return ret;
DRM_DEV_DEBUG_DRIVER(dev, "Panel function check: %s", !!(out[0] & BIT(6)) ? "ok" : "failed");
DRM_DEV_DEBUG_DRIVER(dev, "Panel internal setup: %s", !!(out[0] & BIT(7)) ? "ok" : "failed");
msleep(200); /* docs say 5ms */
#endif
ret = mipi_dsi_dcs_set_display_on(dsi);
if (ret)
return ret;
......@@ -360,9 +322,7 @@ static int jh057n_probe(struct mipi_dsi_device *dsi)
dsi->lanes = 4;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO /* mdss-dsi-panel-type */
/* Vendor says panel does not support burst mode,
but mdss-dsi-traffic-mode says the opposite */
/* | MIPI_DSI_MODE_VIDEO_BURST */
| MIPI_DSI_MODE_VIDEO_BURST
| MIPI_DSI_MODE_VIDEO_SYNC_PULSE
/* the st7703 supports LPM and HSM */
| MIPI_DSI_MODE_LPM
......
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