pci.c 31.4 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
/*
 * iop13xx PCI support
 * Copyright (c) 2005-2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 */

#include <linux/pci.h>
21
#include <linux/slab.h>
22
#include <linux/delay.h>
Alexey Dobriyan's avatar
Alexey Dobriyan committed
23
#include <linux/jiffies.h>
24
#include <linux/export.h>
25
#include <asm/irq.h>
26
#include <mach/hardware.h>
27
#include <asm/sizes.h>
Alexey Dobriyan's avatar
Alexey Dobriyan committed
28
#include <asm/signal.h>
29
#include <asm/mach/pci.h>
30
#include <mach/pci.h>
31 32 33 34 35 36 37 38

#define IOP13XX_PCI_DEBUG 0
#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))

u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
static struct pci_bus *pci_bus_atux = 0;
static struct pci_bus *pci_bus_atue = 0;
39 40
void __iomem *iop13xx_atue_mem_base;
void __iomem *iop13xx_atux_mem_base;
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
size_t iop13xx_atue_mem_size;
size_t iop13xx_atux_mem_size;

EXPORT_SYMBOL(iop13xx_atue_mem_base);
EXPORT_SYMBOL(iop13xx_atux_mem_base);
EXPORT_SYMBOL(iop13xx_atue_mem_size);
EXPORT_SYMBOL(iop13xx_atux_mem_size);

int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
						 access */

/* Scan the initialized busses and ioremap the requested memory range
 */
void iop13xx_map_pci_memory(void)
{
	int atu;
	struct pci_bus *bus;
	struct pci_dev *dev;
	resource_size_t end = 0;

	for (atu = 0; atu < 2; atu++) {
		bus = atu ? pci_bus_atue : pci_bus_atux;
		if (bus) {
			list_for_each_entry(dev, &bus->devices, bus_list) {
				int i;
				int max = 7;

				if (dev->subordinate)
					max = DEVICE_COUNT_RESOURCE;

				for (i = 0; i < max; i++) {
					struct resource *res = &dev->resource[i];
					if (res->flags & IORESOURCE_MEM)
						end = max(res->end, end);
				}
			}

			switch(atu) {
			case 0:
				iop13xx_atux_mem_size =
					(end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;

				/* 16MB align the request */
				if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
					iop13xx_atux_mem_size &= ~(SZ_16M - 1);
					iop13xx_atux_mem_size += SZ_16M;
				}

				if (end) {
91
					iop13xx_atux_mem_base = __arm_ioremap_pfn(
92
					__phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
93
					, 0, iop13xx_atux_mem_size, MT_DEVICE);
94 95
					if (!iop13xx_atux_mem_base) {
						printk("%s: atux allocation "
96
						       "failed\n", __func__);
97 98 99 100
						BUG();
					}
				} else
					iop13xx_atux_mem_size = 0;
101
				PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
102
				__func__, atu, iop13xx_atux_mem_size,
103 104 105 106 107 108 109 110 111 112 113 114 115
				iop13xx_atux_mem_base);
				break;
			case 1:
				iop13xx_atue_mem_size =
					(end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;

				/* 16MB align the request */
				if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
					iop13xx_atue_mem_size &= ~(SZ_16M - 1);
					iop13xx_atue_mem_size += SZ_16M;
				}

				if (end) {
116
					iop13xx_atue_mem_base = __arm_ioremap_pfn(
117
					__phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
118
					, 0, iop13xx_atue_mem_size, MT_DEVICE);
119 120
					if (!iop13xx_atue_mem_base) {
						printk("%s: atue allocation "
121
						       "failed\n", __func__);
122 123 124 125
						BUG();
					}
				} else
					iop13xx_atue_mem_size = 0;
126
				PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
127
				__func__, atu, iop13xx_atue_mem_size,
128 129 130 131
				iop13xx_atue_mem_base);
				break;
			}

132
			printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
133 134 135 136 137 138 139 140 141 142 143 144 145
			atu ? "ATUE" : "ATUX",
			(atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
			SZ_1M,
			atu ? IOP13XX_PCIE_LOWER_MEM_RA :
			IOP13XX_PCIX_LOWER_MEM_RA,
			atu ? iop13xx_atue_mem_base :
			iop13xx_atux_mem_base);
			end = 0;
		}

	}
}

146
static int iop13xx_atu_function(int atu)
147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
{
	int func = 0;
	/* the function number depends on the value of the
	 * IOP13XX_INTERFACE_SEL_PCIX reset strap
	 * see C-Spec section 3.17
	 */
	switch(atu) {
	case IOP13XX_INIT_ATU_ATUX:
		if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
			func = 5;
		else
			func = 0;
		break;
	case IOP13XX_INIT_ATU_ATUE:
		if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
			func = 0;
		else
			func = 5;
		break;
	default:
		BUG();
	}

	return func;
}

/* iop13xx_atux_cfg_address - format a configuration address for atux
 * @bus: Target bus to access
 * @devfn: Combined device number and function number
 * @where: Desired register's address offset
 *
 * Convert the parameters to a configuration address formatted
 * according the PCI-X 2.0 specification
 */
static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
{
	struct pci_sys_data *sys = bus->sysdata;
	u32 addr;

	if (sys->busnr == bus->number)
		addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
	else
		addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;

	addr |=	PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
	addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */

	return addr;
}

/* iop13xx_atue_cfg_address - format a configuration address for atue
 * @bus: Target bus to access
 * @devfn: Combined device number and function number
 * @where: Desired register's address offset
 *
 * Convert the parameters to an address usable by the ATUE_OCCAR
 */
static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
{
	struct pci_sys_data *sys = bus->sysdata;
	u32 addr;

	PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
		bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
	addr = ((u32) bus->number)     << IOP13XX_ATUE_OCCAR_BUS_NUM |
		   ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
		   ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
		   (where & ~0x3);

	if (sys->busnr != bus->number)
		addr |= 1; /* type 1 access */

	return addr;
}

/* This routine checks the status of the last configuration cycle.  If an error
 * was detected it returns >0, else it returns a 0.  The errors being checked
 * are parity, master abort, target abort (master and target).  These types of
Lucas De Marchi's avatar
Lucas De Marchi committed
225
 * errors occur during a config cycle where there is no device, like during
226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260
 * the discovery stage.
 */
static int iop13xx_atux_pci_status(int clear)
{
	unsigned int status;
	int err = 0;

	/*
	 * Check the status registers.
	 */
	status = __raw_readw(IOP13XX_ATUX_ATUSR);
	if (status & IOP_PCI_STATUS_ERROR)
	{
		PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
		if(clear)
			__raw_writew(status & IOP_PCI_STATUS_ERROR,
				IOP13XX_ATUX_ATUSR);
		err = 1;
	}
	status = __raw_readl(IOP13XX_ATUX_ATUISR);
	if (status & IOP13XX_ATUX_ATUISR_ERROR)
	{
		PRINTK("\t\t\tPCI error interrupt:  ATUISR %#08x", status);
		if(clear)
			__raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
				IOP13XX_ATUX_ATUISR);
		err = 1;
	}
	return err;
}

/* Simply write the address register and read the configuration
 * data.  Note that the data dependency on %0 encourages an abort
 * to be detected before we return.
 */
261
static u32 iop13xx_atux_read(unsigned long addr)
262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331
{
	u32 val;

	__asm__ __volatile__(
		"str	%1, [%2]\n\t"
		"ldr	%0, [%3]\n\t"
		"mov	%0, %0\n\t"
		: "=r" (val)
		: "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));

	return val;
}

/* The read routines must check the error status of the last configuration
 * cycle.  If there was an error, the routine returns all hex f's.
 */
static int
iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
		int size, u32 *value)
{
	unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
	u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);

	if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
		__raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
			IOP13XX_XBG_BECSR);
		val = 0xffffffff;
	}

	*value = val;

	return PCIBIOS_SUCCESSFUL;
}

static int
iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
		int size, u32 value)
{
	unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
	u32 val;

	if (size != 4) {
		val = iop13xx_atux_read(addr);
		if (!iop13xx_atux_pci_status(1) == 0)
			return PCIBIOS_SUCCESSFUL;

		where = (where & 3) * 8;

		if (size == 1)
			val &= ~(0xff << where);
		else
			val &= ~(0xffff << where);

		__raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
	} else {
		__raw_writel(addr, IOP13XX_ATUX_OCCAR);
		__raw_writel(value, IOP13XX_ATUX_OCCDR);
	}

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops iop13xx_atux_ops = {
	.read	= iop13xx_atux_read_config,
	.write	= iop13xx_atux_write_config,
};

/* This routine checks the status of the last configuration cycle.  If an error
 * was detected it returns >0, else it returns a 0.  The errors being checked
 * are parity, master abort, target abort (master and target).  These types of
Lucas De Marchi's avatar
Lucas De Marchi committed
332
 * errors occur during a config cycle where there is no device, like during
333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388
 * the discovery stage.
 */
static int iop13xx_atue_pci_status(int clear)
{
	unsigned int status;
	int err = 0;

	/*
	 * Check the status registers.
	 */

	/* standard pci status register */
	status = __raw_readw(IOP13XX_ATUE_ATUSR);
	if (status & IOP_PCI_STATUS_ERROR) {
		PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
		if(clear)
			__raw_writew(status & IOP_PCI_STATUS_ERROR,
				IOP13XX_ATUE_ATUSR);
		err++;
	}

	/* check the normal status bits in the ATUISR */
	status = __raw_readl(IOP13XX_ATUE_ATUISR);
	if (status & IOP13XX_ATUE_ATUISR_ERROR)	{
		PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
		if (clear)
			__raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
				IOP13XX_ATUE_ATUISR);
		err++;

		/* check the PCI-E status if the ATUISR reports an interface error */
		if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
			/* get the unmasked errors */
			status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
					~(__raw_readl(IOP13XX_ATUE_PIE_MSK));

			if (status) {
				PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
					__raw_readl(IOP13XX_ATUE_PIE_STS));
				err++;
			} else {
				PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
					__raw_readl(IOP13XX_ATUE_PIE_STS));
				PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
					__raw_readl(IOP13XX_ATUE_PIE_MSK));
				BUG();
			}

			if(clear)
				__raw_writel(status, IOP13XX_ATUE_PIE_STS);
		}
	}

	return err;
}

389
static int
390
iop13xx_pcie_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
391 392 393 394 395 396 397 398 399 400 401 402
{
	WARN_ON(idsel != 0);

	switch (pin) {
	case 1: return ATUE_INTA;
	case 2: return ATUE_INTB;
	case 3: return ATUE_INTC;
	case 4: return ATUE_INTD;
	default: return -1;
	}
}

403
static u32 iop13xx_atue_read(unsigned long addr)
404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506
{
	u32 val;

	__raw_writel(addr, IOP13XX_ATUE_OCCAR);
	val = __raw_readl(IOP13XX_ATUE_OCCDR);

	rmb();

	return val;
}

/* The read routines must check the error status of the last configuration
 * cycle.  If there was an error, the routine returns all hex f's.
 */
static int
iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
		int size, u32 *value)
{
	u32 val;
	unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);

	/* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
	if (!PCI_SLOT(devfn) || (addr & 1)) {
		val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
		if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
			__raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
				IOP13XX_XBG_BECSR);
			val = 0xffffffff;
		}

		PRINTK("addr=%#0lx, val=%#010x", addr, val);
	} else
		val = 0xffffffff;

	*value = val;

	return PCIBIOS_SUCCESSFUL;
}

static int
iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
		int size, u32 value)
{
	unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
	u32 val;

	if (size != 4) {
		val = iop13xx_atue_read(addr);
		if (!iop13xx_atue_pci_status(1) == 0)
			return PCIBIOS_SUCCESSFUL;

		where = (where & 3) * 8;

		if (size == 1)
			val &= ~(0xff << where);
		else
			val &= ~(0xffff << where);

		__raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
	} else {
		__raw_writel(addr, IOP13XX_ATUE_OCCAR);
		__raw_writel(value, IOP13XX_ATUE_OCCDR);
	}

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops iop13xx_atue_ops = {
	.read	= iop13xx_atue_read_config,
	.write	= iop13xx_atue_write_config,
};

/* When a PCI device does not exist during config cycles, the XScale gets a
 * bus error instead of returning 0xffffffff.  We can't rely on the ATU status
 * bits to tell us that it was indeed a configuration cycle that caused this
 * error especially in the case when the ATUE link is down.  Instead we rely
 * on data from the south XSI bridge to validate the abort
 */
int
iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
	PRINTK("Data abort: address = 0x%08lx "
		    "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
		addr, fsr, regs->ARM_pc, regs->ARM_lr);

	PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
	PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
	PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));

	/*  If it was an imprecise abort, then we need to correct the
	 *  return address to be _after_ the instruction.
	 */
	if (fsr & (1 << 10))
		regs->ARM_pc += 4;

	if (is_atue_occdr_error() || is_atux_occdr_error())
		return 0;
	else
		return 1;
}

/* Scan an IOP13XX PCI bus.  nr selects which ATU we use.
 */
507
struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537
{
	int which_atu;
	struct pci_bus *bus = NULL;

	switch (init_atu) {
	case IOP13XX_INIT_ATU_ATUX:
		which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
		break;
	case IOP13XX_INIT_ATU_ATUE:
		which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
		break;
	case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
		which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
		break;
	default:
		which_atu = 0;
	}

	if (!which_atu) {
		BUG();
		return NULL;
	}

	switch (which_atu) {
	case IOP13XX_INIT_ATU_ATUX:
		if (time_after_eq(jiffies + msecs_to_jiffies(1000),
				  atux_trhfa_timeout))  /* ensure not wrap */
			while(time_before(jiffies, atux_trhfa_timeout))
				udelay(100);

538 539 540
		bus = pci_bus_atux = pci_scan_root_bus(NULL, sys->busnr,
						       &iop13xx_atux_ops,
						       sys, &sys->resources);
541 542
		break;
	case IOP13XX_INIT_ATU_ATUE:
543 544 545
		bus = pci_bus_atue = pci_scan_root_bus(NULL, sys->busnr,
						       &iop13xx_atue_ops,
						       sys, &sys->resources);
546 547 548 549 550 551 552 553 554 555 556 557 558 559 560
		break;
	}

	return bus;
}

/* This function is called from iop13xx_pci_init() after assigning valid
 * values to iop13xx_atue_pmmr_offset.  This is the location for common
 * setup of ATUE for all IOP13XX implementations.
 */
void __init iop13xx_atue_setup(void)
{
	int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
	u32 reg_val;

561 562 563 564 565 566 567 568
#ifdef CONFIG_PCI_MSI
	/* BAR 0 (inbound msi window) */
	__raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
	__raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0);
	__raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0);
	__raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0);
#endif

569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729
	/* BAR 1 (1:1 mapping with Physical RAM) */
	/* Set limit and enable */
	__raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
			IOP13XX_ATUE_IALR1);
	__raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);

	/* Set base at the top of the reserved address space */
	__raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
			PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);

	/* 1:1 mapping with physical ram
	 * (leave big endian byte swap disabled)
	 */
	 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
	 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);

	/* Outbound window 1 (PCIX/PCIE memory window) */
	/* 32 bit Address Space */
	__raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
	/* PA[35:32] */
	__raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
			(IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
			IOP13XX_ATUE_OUMBAR1);

	/* Setup the I/O Bar
	 * A[35-16] in 31-12
	 */
	__raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
		IOP13XX_ATUE_OIOBAR);
	__raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);

	/* clear startup errors */
	iop13xx_atue_pci_status(1);

	/* OIOBAR function number
	 */
	reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
	reg_val &= ~0x7;
	reg_val |= func;
	__raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);

	/* OUMBAR function numbers
	 */
	reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
	reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
			IOP13XX_ATU_OUMBAR_FUNC_NUM);
	reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
	__raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);

	reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
	reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
			IOP13XX_ATU_OUMBAR_FUNC_NUM);
	reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
	__raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);

	reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
	reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
			IOP13XX_ATU_OUMBAR_FUNC_NUM);
	reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
	__raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);

	reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
	reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
			IOP13XX_ATU_OUMBAR_FUNC_NUM);
	reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
	__raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);

	/* Enable inbound and outbound cycles
	 */
	reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
	reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
			PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
	__raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);

	reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
	reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
			IOP13XX_ATUE_ATUCR_IVM;
	__raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
}

void __init iop13xx_atue_disable(void)
{
	u32 reg_val;

	__raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
	__raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);

	/* wait for cycles to quiesce */
	while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
					     IOP13XX_ATUE_PCSR_IN_Q_BUSY |
					     IOP13XX_ATUE_PCSR_LLRB_BUSY))
		cpu_relax();

	/* BAR 0 ( Disabled ) */
	__raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
	__raw_writel(0x0, IOP13XX_ATUE_IABAR0);
	__raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
	__raw_writel(0x0, IOP13XX_ATUE_IATVR0);
	__raw_writel(0x0, IOP13XX_ATUE_IALR0);
	reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
	reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
	__raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);

	/* BAR 1 ( Disabled ) */
	__raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
	__raw_writel(0x0, IOP13XX_ATUE_IABAR1);
	__raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
	__raw_writel(0x0, IOP13XX_ATUE_IATVR1);
	__raw_writel(0x0, IOP13XX_ATUE_IALR1);
	reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
	reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
	__raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);

	/* BAR 2 ( Disabled ) */
	__raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
	__raw_writel(0x0, IOP13XX_ATUE_IABAR2);
	__raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
	__raw_writel(0x0, IOP13XX_ATUE_IATVR2);
	__raw_writel(0x0, IOP13XX_ATUE_IALR2);
	reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
	reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
	__raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);

	/* BAR 3 ( Disabled ) */
	reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
	reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
	__raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);

	/* Setup the I/O Bar
	 * A[35-16] in 31-12
	 */
	__raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
			IOP13XX_ATUE_OIOBAR);
	__raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
}

/* This function is called from iop13xx_pci_init() after assigning valid
 * values to iop13xx_atux_pmmr_offset.  This is the location for common
 * setup of ATUX for all IOP13XX implementations.
 */
void __init iop13xx_atux_setup(void)
{
	u32 reg_val;
	int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);

	/* Take PCI-X bus out of reset if bootloader hasn't already.
	 * According to spec, we should wait for 2^25 PCI clocks to meet
	 * the PCI timing parameter Trhfa (RST# high to first access).
	 * This is rarely necessary and often ignored.
	 */
	reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
	if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
		int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
		msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
		__raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
				IOP13XX_ATUX_PCSR);
		atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
	}
	else
		atux_trhfa_timeout = jiffies;

730 731 732 733 734 735 736 737
#ifdef CONFIG_PCI_MSI
	/* BAR 0 (inbound msi window) */
	__raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
	__raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0);
	__raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0);
	__raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0);
#endif

738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970
	/* BAR 1 (1:1 mapping with Physical RAM) */
	/* Set limit and enable */
	__raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
			IOP13XX_ATUX_IALR1);
	__raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);

	/* Set base at the top of the reserved address space */
	__raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
			PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);

	/* 1:1 mapping with physical ram
	 * (leave big endian byte swap disabled)
	 */
	__raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
	__raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);

	/* Outbound window 1 (PCIX/PCIE memory window) */
	/* 32 bit Address Space */
	__raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
	/* PA[35:32] */
	__raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
			IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
			IOP13XX_ATUX_OUMBAR1);

	/* Setup the I/O Bar
	 * A[35-16] in 31-12
	 */
	__raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
		IOP13XX_ATUX_OIOBAR);
	__raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);

	/* clear startup errors */
	iop13xx_atux_pci_status(1);

	/* OIOBAR function number
	 */
	reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
	reg_val &= ~0x7;
	reg_val |= func;
	__raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);

	/* OUMBAR function numbers
	 */
	reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
	reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
			IOP13XX_ATU_OUMBAR_FUNC_NUM);
	reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
	__raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);

	reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
	reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
			IOP13XX_ATU_OUMBAR_FUNC_NUM);
	reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
	__raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);

	reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
	reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
			IOP13XX_ATU_OUMBAR_FUNC_NUM);
	reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
	__raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);

	reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
	reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
			IOP13XX_ATU_OUMBAR_FUNC_NUM);
	reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
	__raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);

	/* Enable inbound and outbound cycles
	 */
	reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
	reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
		        PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
	__raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);

	reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
	reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
	__raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
}

void __init iop13xx_atux_disable(void)
{
	u32 reg_val;

	__raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
	__raw_writel(0x0, IOP13XX_ATUX_ATUCR);

	/* wait for cycles to quiesce */
	while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
				     IOP13XX_ATUX_PCSR_IN_Q_BUSY))
		cpu_relax();

	/* BAR 0 ( Disabled ) */
	__raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
	__raw_writel(0x0, IOP13XX_ATUX_IABAR0);
	__raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
	__raw_writel(0x0, IOP13XX_ATUX_IATVR0);
	__raw_writel(0x0, IOP13XX_ATUX_IALR0);
	reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
	reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
	__raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);

	/* BAR 1 ( Disabled ) */
	__raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
	__raw_writel(0x0, IOP13XX_ATUX_IABAR1);
	__raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
	__raw_writel(0x0, IOP13XX_ATUX_IATVR1);
	__raw_writel(0x0, IOP13XX_ATUX_IALR1);
	reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
	reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
	__raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);

	/* BAR 2 ( Disabled ) */
	__raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
	__raw_writel(0x0, IOP13XX_ATUX_IABAR2);
	__raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
	__raw_writel(0x0, IOP13XX_ATUX_IATVR2);
	__raw_writel(0x0, IOP13XX_ATUX_IALR2);
	reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
	reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
	__raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);

	/* BAR 3 ( Disabled ) */
	__raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
	__raw_writel(0x0, IOP13XX_ATUX_IABAR3);
	__raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
	__raw_writel(0x0, IOP13XX_ATUX_IATVR3);
	__raw_writel(0x0, IOP13XX_ATUX_IALR3);
	reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
	reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
	__raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);

	/* Setup the I/O Bar
	* A[35-16] in 31-12
	*/
	__raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
			IOP13XX_ATUX_OIOBAR);
	__raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
}

void __init iop13xx_set_atu_mmr_bases(void)
{
	/* Based on ESSR0, determine the ATU X/E offsets */
	switch(__raw_readl(IOP13XX_ESSR0) &
		(IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
	/* both asserted */
	case 0:
		iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
		iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
		break;
	/* IOP13XX_CONTROLLER_ONLY = deasserted
	 * IOP13XX_INTERFACE_SEL_PCIX = asserted
	 */
	case IOP13XX_CONTROLLER_ONLY:
		iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
		iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
		break;
	/* IOP13XX_CONTROLLER_ONLY = asserted
	 * IOP13XX_INTERFACE_SEL_PCIX = deasserted
	 */
	case IOP13XX_INTERFACE_SEL_PCIX:
		iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
		iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
		break;
	/* both deasserted */
	case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
		iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
		iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
		break;
	default:
		BUG();
	}
}

void __init iop13xx_atu_select(struct hw_pci *plat_pci)
{
	int i;

	/* set system defaults
	 * note: if "iop13xx_init_atu=" is specified this autodetect
	 * sequence will be bypassed
	 */
	if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
		/* check for single/dual interface */
		if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
			/* ATUE must be present check the device id
			 * to see if ATUX is present.
			 */
			init_atu |= IOP13XX_INIT_ATU_ATUE;
			switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
			case 0x70:
			case 0x80:
			case 0xc0:
				init_atu |= IOP13XX_INIT_ATU_ATUX;
				break;
			}
		} else {
			/* ATUX must be present check the device id
			 * to see if ATUE is present.
			 */
			init_atu |= IOP13XX_INIT_ATU_ATUX;
			switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
			case 0x70:
			case 0x80:
			case 0xc0:
				init_atu |= IOP13XX_INIT_ATU_ATUE;
				break;
			}
		}

		/* check central resource and root complex capability */
		if (init_atu & IOP13XX_INIT_ATU_ATUX)
			if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
				IOP13XX_ATUX_PCSR_CENTRAL_RES))
				init_atu &= ~IOP13XX_INIT_ATU_ATUX;

		if (init_atu & IOP13XX_INIT_ATU_ATUE)
			if (__raw_readl(IOP13XX_ATUE_PCSR) &
				IOP13XX_ATUE_PCSR_END_POINT)
				init_atu &= ~IOP13XX_INIT_ATU_ATUE;
	}

	for (i = 0; i < 2; i++) {
		if((init_atu & (1 << i)) == (1 << i))
			plat_pci->nr_controllers++;
	}
}

void __init iop13xx_pci_init(void)
{
	/* clear pre-existing south bridge errors */
	__raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);

	/* Setup the Min Address for PCI memory... */
971
	pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
972 973 974 975 976 977 978 979 980 981 982 983 984 985 986

	/* if Linux is given control of an ATU
	 * clear out its prior configuration,
	 * otherwise do not touch the registers
	 */
	if (init_atu & IOP13XX_INIT_ATU_ATUE) {
		iop13xx_atue_disable();
		iop13xx_atue_setup();
	}

	if (init_atu & IOP13XX_INIT_ATU_ATUX) {
		iop13xx_atux_disable();
		iop13xx_atux_setup();
	}

987
	hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
988 989 990
			"imprecise external abort");
}

Simon Arlott's avatar
Simon Arlott committed
991
/* initialize the pci memory space.  handle any combination of
992 993 994 995 996 997 998 999 1000 1001 1002
 * atue and atux enabled/disabled
 */
int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
{
	struct resource *res;
	int which_atu;
	u32 pcixsr, pcsr;

	if (nr > 1)
		return 0;

1003
	res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026
	if (!res)
		panic("PCI: unable to alloc resources");


	/* 'nr' assumptions:
	 * ATUX is always 0
	 * ATUE is 1 when ATUX is also enabled
	 * ATUE is 0 when ATUX is disabled
	 */
	switch(init_atu) {
	case IOP13XX_INIT_ATU_ATUX:
		which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
		break;
	case IOP13XX_INIT_ATU_ATUE:
		which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
		break;
	case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
		which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
		break;
	default:
		which_atu = 0;
	}

Alan Cox's avatar
Alan Cox committed
1027 1028
	if (!which_atu) {
		kfree(res);
1029
		return 0;
Alan Cox's avatar
Alan Cox committed
1030
	}
1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041

	switch(which_atu) {
	case IOP13XX_INIT_ATU_ATUX:
		pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
		pcixsr &= ~0xffff;
		pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
			  0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
			  iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
				  << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
		__raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);

1042
		pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
1043

1044 1045 1046 1047
		res->start = IOP13XX_PCIX_LOWER_MEM_RA;
		res->end   = IOP13XX_PCIX_UPPER_MEM_RA;
		res->name  = "IQ81340 ATUX PCI Memory Space";
		res->flags = IORESOURCE_MEM;
1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058
		sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
		break;
	case IOP13XX_INIT_ATU_ATUE:
		/* Note: the function number field in the PCSR is ro */
		pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
		pcsr &= ~(0xfff8 << 16);
		pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
				0 << IOP13XX_ATUE_PCSR_DEV_NUM;

		__raw_writel(pcsr, IOP13XX_ATUE_PCSR);

1059
		pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
1060

1061 1062 1063 1064
		res->start = IOP13XX_PCIE_LOWER_MEM_RA;
		res->end   = IOP13XX_PCIE_UPPER_MEM_RA;
		res->name  = "IQ81340 ATUE PCI Memory Space";
		res->flags = IORESOURCE_MEM;
1065 1066 1067 1068
		sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
		sys->map_irq = iop13xx_pcie_map_irq;
		break;
	default:
Alan Cox's avatar
Alan Cox committed
1069
		kfree(res);
1070 1071 1072
		return 0;
	}

1073
	request_resource(&iomem_resource, res);
1074

1075
	pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119

	return 1;
}

u16 iop13xx_dev_id(void)
{
	if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
		return __raw_readw(IOP13XX_ATUE_DID);
	else
		return __raw_readw(IOP13XX_ATUX_DID);
}

static int __init iop13xx_init_atu_setup(char *str)
{
        init_atu = IOP13XX_INIT_ATU_NONE;
        if (str) {
                while (*str != '\0') {
                        switch (*str) {
                        case 'x':
                        case 'X':
                                init_atu |= IOP13XX_INIT_ATU_ATUX;
                                init_atu &= ~IOP13XX_INIT_ATU_NONE;
                                break;
                        case 'e':
                        case 'E':
                                init_atu |= IOP13XX_INIT_ATU_ATUE;
                                init_atu &= ~IOP13XX_INIT_ATU_NONE;
                                break;
                        case ',':
                        case '=':
                                break;
                        default:
                                PRINTK("\"iop13xx_init_atu\" malformed at "
                                            "character: \'%c\'", *str);
                                *(str + 1) = '\0';
                                init_atu = IOP13XX_INIT_ATU_DEFAULT;
                        }
                        str++;
                }
        }
        return 1;
}

__setup("iop13xx_init_atu", iop13xx_init_atu_setup);