pcie.c 6.4 KB
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/*
 * arch/arm/mach-kirkwood/pcie.c
 *
 * PCIe functions for Marvell Kirkwood SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <video/vga.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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#include <plat/pcie.h>
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#include <mach/bridge-regs.h>
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#include <plat/addr-map.h>
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#include "common.h"

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static void kirkwood_enable_pcie_clk(const char *port)
{
	struct clk *clk;

	clk = clk_get_sys("pcie", port);
	if (IS_ERR(clk)) {
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		pr_err("PCIE clock %s missing\n", port);
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		return;
	}
	clk_prepare_enable(clk);
	clk_put(clk);
}

/* This function is called very early in the boot when probing the
   hardware to determine what we actually are, and what rate tclk is
   ticking at. Hence calling kirkwood_enable_pcie_clk() is not
   possible since the clk tree has not been created yet. */
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void kirkwood_enable_pcie(void)
{
	u32 curr = readl(CLOCK_GATING_CTRL);
	if (!(curr & CGC_PEX0))
		writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
}

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void kirkwood_pcie_id(u32 *dev, u32 *rev)
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{
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	kirkwood_enable_pcie();
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	*dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
	*rev = orion_pcie_rev(PCIE_VIRT_BASE);
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}
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struct pcie_port {
	u8			root_bus_nr;
	void __iomem		*base;
	spinlock_t		conf_lock;
	int			irq;
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	struct resource		res;
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};
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static int pcie_port_map[2];
static int num_pcie_ports;

static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
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{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
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	if (bus == pp->root_bus_nr && dev == 0)
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		return 1;

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	if (!orion_pcie_link_up(pp->base))
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		return 0;

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	if (bus == pp->root_bus_nr && dev != 1)
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		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
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	struct pci_sys_data *sys = bus->sysdata;
	struct pcie_port *pp = sys->private_data;
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	unsigned long flags;
	int ret;

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	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
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		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

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	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);
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	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
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	struct pci_sys_data *sys = bus->sysdata;
	struct pcie_port *pp = sys->private_data;
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	unsigned long flags;
	int ret;

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	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
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		return PCIBIOS_DEVICE_NOT_FOUND;

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	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);
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	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};

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static void __init pcie0_ioresources_init(struct pcie_port *pp)
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{
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	pp->base = PCIE_VIRT_BASE;
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	pp->irq	= IRQ_KIRKWOOD_PCIE;
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	/*
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	 * IORESOURCE_MEM
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	 */
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	pp->res.name = "PCIe 0 MEM";
	pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
	pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	pp->res.flags = IORESOURCE_MEM;
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}

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static void __init pcie1_ioresources_init(struct pcie_port *pp)
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{
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	pp->base = PCIE1_VIRT_BASE;
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	pp->irq	= IRQ_KIRKWOOD_PCIE1;
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	/*
	 * IORESOURCE_MEM
	 */
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	pp->res.name = "PCIe 1 MEM";
	pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
	pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
	pp->res.flags = IORESOURCE_MEM;
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}

static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
{
	struct pcie_port *pp;
	int index;

	if (nr >= num_pcie_ports)
		return 0;

	index = pcie_port_map[nr];
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	pr_info("PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
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	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
	if (!pp)
		panic("PCIe: failed to allocate pcie_port data");
	sys->private_data = pp;
	pp->root_bus_nr = sys->busnr;
	spin_lock_init(&pp->conf_lock);

	switch (index) {
	case 0:
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		kirkwood_enable_pcie_clk("0");
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		pcie0_ioresources_init(pp);
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		pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
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		break;
	case 1:
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		kirkwood_enable_pcie_clk("1");
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		pcie1_ioresources_init(pp);
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		pci_ioremap_io(SZ_64K * sys->busnr,
			       KIRKWOOD_PCIE1_IO_PHYS_BASE);
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		break;
	default:
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		panic("PCIe setup: invalid controller %d", index);
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	}

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	if (request_resource(&iomem_resource, &pp->res))
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		panic("Request PCIe%d Memory resource failed\n", index);

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	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
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	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);

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	orion_pcie_setup(pp->base);
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	return 1;
}

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/*
 * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
 * is operating as a root complex this needs to be switched to
 * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
 * the device. Decoding setup is handled by the orion code.
 */
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static void rc_pci_fixup(struct pci_dev *dev)
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{
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

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		dev->class &= 0xff;
		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
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		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

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static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
	u8 pin)
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{
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	struct pci_sys_data *sys = dev->sysdata;
	struct pcie_port *pp = sys->private_data;
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	return pp->irq;
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}

static struct hw_pci kirkwood_pci __initdata = {
	.setup		= kirkwood_pcie_setup,
	.map_irq	= kirkwood_pcie_map_irq,
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	.ops            = &pcie_ops,
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};

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static void __init add_pcie_port(int index, void __iomem *base)
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{
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	pr_info("Kirkwood PCIe port %d: ", index);
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	if (orion_pcie_link_up(base)) {
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		pr_info("link up\n");
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		pcie_port_map[num_pcie_ports++] = index;
	} else
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		pr_info("link down, ignoring\n");
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}

void __init kirkwood_pcie_init(unsigned int portmask)
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{
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	vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;

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	if (portmask & KW_PCIE0)
		add_pcie_port(0, PCIE_VIRT_BASE);

	if (portmask & KW_PCIE1)
		add_pcie_port(1, PCIE1_VIRT_BASE);

	kirkwood_pci.nr_controllers = num_pcie_ports;
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	pci_common_init(&kirkwood_pci);
}