pm.c 2.81 KB
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/*
 * Copyright 2008 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 */

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#include <linux/init.h>
#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/atomic.h>
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#include "cns3xxx.h"
#include "pm.h"
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#include "core.h"
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void cns3xxx_pwr_clk_en(unsigned int block)
{
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	u32 reg = __raw_readl(PM_CLK_GATE_REG);

	reg |= (block & PM_CLK_GATE_REG_MASK);
	__raw_writel(reg, PM_CLK_GATE_REG);
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}
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EXPORT_SYMBOL(cns3xxx_pwr_clk_en);

void cns3xxx_pwr_clk_dis(unsigned int block)
{
	u32 reg = __raw_readl(PM_CLK_GATE_REG);

	reg &= ~(block & PM_CLK_GATE_REG_MASK);
	__raw_writel(reg, PM_CLK_GATE_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
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void cns3xxx_pwr_power_up(unsigned int block)
{
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	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);

	reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
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	/* Wait for 300us for the PLL output clock locked. */
	udelay(300);
};
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EXPORT_SYMBOL(cns3xxx_pwr_power_up);
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void cns3xxx_pwr_power_down(unsigned int block)
{
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	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);

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	/* write '1' to power down */
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	reg |= (block & CNS3XXX_PWR_PLL_ALL);
	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
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};
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EXPORT_SYMBOL(cns3xxx_pwr_power_down);
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static void cns3xxx_pwr_soft_rst_force(unsigned int block)
{
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	u32 reg = __raw_readl(PM_SOFT_RST_REG);

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	/*
	 * bit 0, 28, 29 => program low to reset,
	 * the other else program low and then high
	 */
	if (block & 0x30000001) {
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		reg &= ~(block & PM_SOFT_RST_REG_MASK);
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	} else {
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		reg &= ~(block & PM_SOFT_RST_REG_MASK);
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		__raw_writel(reg, PM_SOFT_RST_REG);
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		reg |= (block & PM_SOFT_RST_REG_MASK);
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	}
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	__raw_writel(reg, PM_SOFT_RST_REG);
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}
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EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
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void cns3xxx_pwr_soft_rst(unsigned int block)
{
	static unsigned int soft_reset;

	if (soft_reset & block) {
		/* SPI/I2C/GPIO use the same block, reset once. */
		return;
	} else {
		soft_reset |= block;
	}
	cns3xxx_pwr_soft_rst_force(block);
}
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EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
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void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
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{
	/*
	 * To reset, we hit the on-board reset register
	 * in the system FPGA.
	 */
	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
}

/*
 * cns3xxx_cpu_clock - return CPU/L2 clock
 *  aclk: cpu clock/2
 *  hclk: cpu clock/4
 *  pclk: cpu clock/8
 */
int cns3xxx_cpu_clock(void)
{
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	u32 reg = __raw_readl(PM_CLK_CTRL_REG);
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	int cpu;
	int cpu_sel;
	int div_sel;

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	cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
	div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
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	cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;

	return cpu;
}
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EXPORT_SYMBOL(cns3xxx_cpu_clock);
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atomic_t usb_pwr_ref = ATOMIC_INIT(0);
EXPORT_SYMBOL(usb_pwr_ref);