s5k3l6xx.c 36.4 KB
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// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Samsung S5K3L6XX 1/3" 13M CMOS Image Sensor.
 *
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 * Copyright (C) 2020-2021 Purism SPC
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 *
 * Based on S5K5BAF driver
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 * Copyright (C) 2013, Samsung Electronics Co., Ltd.
 * Andrzej Hajda <a.hajda@samsung.com>
 *
 * Based on S5K6AA driver authored by Sylwester Nawrocki
 * Copyright (C) 2013, Samsung Electronics Co., Ltd.
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 */

#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/media.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/of_graph.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/pm.h>
#include <linux/slab.h>

#include <media/media-entity.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-mediabus.h>
#include <media/v4l2-fwnode.h>

static int debug;
module_param(debug, int, 0644);

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#define S5K3L6XX_DRIVER_NAME		"s5k3l6xx"
#define S5K3L6XX_DEFAULT_MCLK_FREQ	24000000U
#define S5K3L6XX_CLK_NAME		"mclk"
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#define S5K3L6XX_REG_MODEL_ID_L		0x0000
#define S5K3L6XX_REG_MODEL_ID_H		0x0001
#define S5K3L6XX_MODEL_ID_L		0x30
#define S5K3L6XX_MODEL_ID_H		0xc6
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#define S5K3L6XX_REG_REVISION_NUMBER	0x0002
#define S5K3L6XX_REVISION_NUMBER	0xb0
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#define S5K3L6XX_REG_FRAME_COUNT	0x0005
#define S5K3L6XX_REG_LANE_MODE		0x0114
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#define S5K3L6XX_REG_FINE_INTEGRATION_TIME		0x0200 // 2 bytes
#define S5K3L6XX_REG_COARSE_INTEGRATION_TIME		0x0202 // 2 bytes
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#define S5K3L6XX_REG_ANALOG_GAIN		0x0204 // 2 bytes
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#define S5K3L6XX_REG_DIGITAL_GAIN		0x020e // 2 bytes
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#define S5K3L6XX_REG_TEST_PATTERN_MODE	0x0601
#define S5K3L6XX_TEST_PATTERN_SOLID_COLOR	0x01
#define S5K3L6XX_TEST_PATTERN_COLOR_BAR	0x02
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#define S5K3L6XX_REG_TEST_DATA_RED	0x0602
#define S5K3L6XX_REG_TEST_DATA_GREENR	0x0604
#define S5K3L6XX_REG_TEST_DATA_BLUE	0x0606
#define S5K3L6XX_REG_TEST_DATA_GREENB	0x0608
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#define S5K3L6XX_REG_AF			0x3403
#define S5K3L6XX_REG_AF_BIT_FILTER	0b100

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#define S5K3L6XX_REG_MODE_SELECT	0x100
#define S5K3L6XX_MODE_STREAMING		0x1
#define S5K3L6XX_MODE_STANDBY		0x0
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#define S5K3L6XX_REG_DATA_FORMAT	0x0112
#define S5K3L6XX_DATA_FORMAT_RAW8	0x0808
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#define S5K3L6XX_CIS_WIDTH		4208
#define S5K3L6XX_CIS_HEIGHT		3120
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struct s5k3l6xx_reg {
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	u16 address;
	u16 val;
	// Size of a single write.
	u8 size;
};

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// Downscaled 1:4 in both directions.
// Spans the entire sensor. Fps unknown.
// Relies on defaults to be set correctly.
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static const struct s5k3l6xx_reg frame_1052x780px_8bit_xfps_2lane[] = {
	// extclk freq 25MHz (doesn't seem to matter)
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	{ 0x0136, 0x1900,       2 },

	// x_output_size
	{ 0x034c, 0x041c,       2 },
	// line length in pixel clocks. x_output_size * 1.16
	// if using binning multiply x_output_size by the binning factor first
	{ 0x0342, 0x1320,       2 },
	// y_output_size
	{ 0x034e, 0x030c,       2 },

	// op_pll_multiplier, default 0064
	{ 0x030e, 0x0036,       2 },

	// y_addr_start
	{ 0x0346, 0x0000,       2 },
	// end = y_output_size * binning_factor + y_addr_start
	{ 0x034a, 0x0c30,       2 },
	// x_addr_start
	{ 0x0344, 0x0008,       2 },
	// end = x_output_size * binning_factor + x_addr_start - 1
	{ 0x0348, 0x1077,       2 },

	// binning enable
	{ 0x0900, 0x01, 1 },
	// type: 1/?x, 1/?y, full binning when matching skips
	{ 0x0901, 0x44, 1 },
	// y_odd_inc
	{ 0x0387, 0x07, 1 },
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	// Noise reduction
	// The last 3 bits (0x0007) control some global brightness/noise pattern.
	// They work slightly differently depending on the value of 307b:80
	// It's not strictly necessary here,
	// as the sensor seems to do the same correction without asking at 1:4 binning,
	// but added to formalize the default value.
	{ 0x3074, 0x0974, 2},
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};

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// Downscaled 1:2 in both directions.
// Spans the entire sensor. Fps unknown.
// Relies on defaults to be set correctly.
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static const struct s5k3l6xx_reg frame_2104x1560px_8bit_xfps_2lane[] = {
	// extclk freq 25MHz (doesn't seem to matter)
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	{ 0x0136, 0x1900,       2 },

	// x_output_size
	{ 0x034c, 0x0838,       2 },
	// y_output_size
	{ 0x034e, 0x0618,       2 },
	// op_pll_multiplier, default 0064
	// 0036 is good for 175MHz on mipi side, although it makes the source clock 216MHz (double-check)
	// 0042 ok for 200MHz
	// 0052 ok for 250MHz
	{ 0x030e, 0x0053,       2 },

	// y_addr_start
	{ 0x0346, 0x0000,       2 },
	// end
	{ 0x034a, 0x0c30,       2 },
	// x_addr_start
	{ 0x0344, 0x0000,       2 },
	// end to match sensor
	{ 0x0348, 0x1068,       2 },

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	// binning in 1:2 mode seems to average out focus pixels.
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	// binning enable
	{ 0x0900, 0x01, 1 },
	// type: 1/?x, 1/?y, full binning when matching skips
	{ 0x0901, 0x22, 1 },
	// x binning skips 8-pixel bocks, making it useless
	// y_odd_inc
	{ 0x0387, 0x03, 1 },
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	// Noise reduction
	// The last 3 bits (0x0007) control some global brightness/noise pattern.
	// They work slightly differently depending on the value of 307b:80
	// 0x0972 makes focus pixels appear.
	{ 0x3074, 0x0974, 2}, // 74, 75, 76, 77 all good for binning 1:2.
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	// filter out autofocus pixels
	// FIXME: this should be behind a custom control instead
	{ 0x3403, 0x42 | S5K3L6XX_REG_AF_BIT_FILTER, 1 },
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};

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// Not scaled.
// Spans the entire sensor. Fps unknown.
// Relies on defaults to be set correctly.
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static const struct s5k3l6xx_reg frame_4208x3120px_8bit_xfps_2lane[] = {
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	// extclk freq (doesn't actually matter)
	{ 0x0136, 0x1900,       2 },

	// x_output_size
	{ 0x034c, 0x1070,       2 },
	// y_output_size
	{ 0x034e, 0x0c30,       2 },
	// op_pll_multiplier, default 0064
	// 0036 is good (max) for 175MHz on mipi side, although it makes the source clock 216MHz (double-check)
	// 0042 ok for 200MHz
	// 0052 ok for 250MHz
	// 006c for 333Mhz
	{ 0x030e, 0x0033,       2 },

	// y_addr_start
	{ 0x0346, 0x0000,       2 },
	// end
	{ 0x034a, 0x0c30,       2 },
	// x_addr_start
	{ 0x0344, 0x0000,       2 },
	// end to match sensor
	{ 0x0348, 0x1068,       2 },
	// line length in pixel clocks. This is a slow mode.
	{ 0x0342, 0x3600,       2 },
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	// Noise reduction
	// The last 3 bits (0x0007) control some global brightness/noise pattern.
	// They work slightly differently depending on the value of 307b:80
	{ 0x3074, 0x0977, 2}, // 74, 75, 76, 77 all good for binning 1:!, might introduce banding.
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	// filter out autofocus pixels
	// FIXME: this should be behind a custom control instead
	{ 0x3403, 0x42 | S5K3L6XX_REG_AF_BIT_FILTER, 1 },
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};

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struct s5k3l6xx_gpio {
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	int gpio;
	int level;
};

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enum s5k3l6xx_gpio_id {
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	RST,
	NUM_GPIOS,
};

#define PAD_CIS 0
#define PAD_OUT 1
#define NUM_CIS_PADS 1
#define NUM_ISP_PADS 2


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struct s5k3l6xx_frame {
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	char *name;
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	u32 width;
	u32 height;
	u32 code;
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	const struct s5k3l6xx_reg  *streamregs;
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	u16 streamregcount;
};

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struct s5k3l6xx_ctrls {
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	struct v4l2_ctrl_handler handler;
	struct { /* Auto / manual white balance cluster */
		struct v4l2_ctrl *awb;
		struct v4l2_ctrl *gain_red;
		struct v4l2_ctrl *gain_blue;
	};
	struct { /* Mirror cluster */
		struct v4l2_ctrl *hflip;
		struct v4l2_ctrl *vflip;
	};
	struct { /* Auto exposure / manual exposure and gain cluster */
		struct v4l2_ctrl *auto_exp;
		struct v4l2_ctrl *exposure;
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		struct v4l2_ctrl *analog_gain;
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		struct v4l2_ctrl *digital_gain;
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	};
};

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struct regstable_entry {
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	u16 address;
	u8 value;
};

#define REGSTABLE_SIZE 4096

struct regstable {
	unsigned entry_count;
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	struct regstable_entry entries[REGSTABLE_SIZE];
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};

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struct s5k3l6xx {
	struct s5k3l6xx_gpio gpios[NUM_GPIOS];
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	enum v4l2_mbus_type bus_type;
	u8 nlanes;
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	struct regulator *supply;
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	struct clk *clock;
	u32 mclk_frequency;

	struct v4l2_subdev cis_sd;
	struct media_pad cis_pad;

	struct v4l2_subdev sd;
	struct media_pad pads[NUM_ISP_PADS];

	/* protects the struct members below */
	struct mutex lock;

	int error;

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	/* Currently selected frame format */
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	const struct s5k3l6xx_frame *frame_fmt;
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	struct s5k3l6xx_ctrls ctrls;
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	/* Solid color test pattern is in effect,
	 * write needs to happen after color choice writes.
	 * It doesn't seem that controls guarantee any order of application. */
	unsigned int apply_test_solid:1;

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	unsigned int streaming:1;
	unsigned int apply_cfg:1;
	unsigned int apply_crop:1;
	unsigned int valid_auto_alg:1;
	unsigned int power;
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	u8 debug_frame; // Enables any size, sets empty debug frame.
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	/* For debug address temporary value */
	u16 debug_address;
	struct regstable debug_regs;
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};

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static const struct s5k3l6xx_reg no_regs[0] = {};
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static const struct s5k3l6xx_frame s5k3l6xx_frame_debug = {
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	.name = "debug_empty",
	.width = 640, .height = 480,
	.streamregs = no_regs,
	.streamregcount = 0,
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	.code = MEDIA_BUS_FMT_SGRBG8_1X8,
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};

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// Frame sizes are only available in RAW, so this effectively replaces pixfmt.
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// Supported frame configurations.
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static const struct s5k3l6xx_frame s5k3l6xx_frames[] = {
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	{
		.name = "1:4 8bpp ?fps",
		.width = 1052, .height = 780,
		.streamregs = frame_1052x780px_8bit_xfps_2lane,
		.streamregcount = ARRAY_SIZE(frame_1052x780px_8bit_xfps_2lane),
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		.code = MEDIA_BUS_FMT_SGRBG8_1X8,
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	},
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	{
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		.name = "1:2 8bpp +fps",
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		.width = 2104, .height = 1560,
		.streamregs = frame_2104x1560px_8bit_xfps_2lane,
		.streamregcount = ARRAY_SIZE(frame_2104x1560px_8bit_xfps_2lane),
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		.code = MEDIA_BUS_FMT_SGRBG8_1X8,
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	},
	{
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		.name = "1:1 8bpp ?fps",
		.width = 4208, .height = 3120,
		.streamregs = frame_4208x3120px_8bit_xfps_2lane,
		.streamregcount = ARRAY_SIZE(frame_4208x3120px_8bit_xfps_2lane),
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		.code = MEDIA_BUS_FMT_SGRBG8_1X8,
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	},
};

static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
{
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	return &container_of(ctrl->handler, struct s5k3l6xx, ctrls.handler)->sd;
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}

static inline bool s5k5baf_is_cis_subdev(struct v4l2_subdev *sd)
{
	return sd->entity.function == MEDIA_ENT_F_CAM_SENSOR;
}

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static inline struct s5k3l6xx *to_s5k3l6xx(struct v4l2_subdev *sd)
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{
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	return container_of(sd, struct s5k3l6xx, sd);
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}

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static u8 __s5k3l6xx_i2c_read(struct s5k3l6xx *state, u16 addr)
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{
	struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
	__be16 w;
	u8 res;
	struct i2c_msg msg[] = {
		{ .addr = c->addr, .flags = 0,
		  .len = 2, .buf = (u8 *)&w },
		{ .addr = c->addr, .flags = I2C_M_RD,
		  .len = 1, .buf = (u8 *)&res },
	};
	int ret;

	if (state->error)
		return 0;

	w = cpu_to_be16(addr);
	ret = i2c_transfer(c->adapter, msg, 2);

	if (ret != 2) {
		v4l2_err(c, "i2c_read: error during transfer (%d)\n", ret);
		state->error = ret;
	}
	return res;
}

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static u8 s5k3l6xx_i2c_read(struct s5k3l6xx *state, u16 addr)
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{
	struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
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	u8 res = __s5k3l6xx_i2c_read(state, addr);
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	v4l2_dbg(3, debug, c, "i2c_read: 0x%04x : 0x%02x\n", addr, res);
	return res;
}

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static void s5k3l6xx_i2c_write(struct s5k3l6xx *state, u16 addr, u8 val)
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{
	struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
	u8 buf[3] = { addr >> 8, addr & 0xFF, val };

	struct i2c_msg msg[] = {
		{ .addr = c->addr, .flags = 0,
		  .len = 3, .buf = buf },
	};
	int ret;
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	int actual;
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	if (state->error)
		return;

	ret = i2c_transfer(c->adapter, msg, 1);

	v4l2_dbg(3, debug, c, "i2c_write to 0x%04x : 0x%02x\n", addr, val);

	if (ret != 1) {
		v4l2_err(c, "i2c_write: error during transfer (%d)\n", ret);
		state->error = ret;
	}
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	// Not sure if actually needed. So really debugging code at the moment.
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	actual = s5k3l6xx_i2c_read(state, addr);
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	if (actual != val) {
		v4l2_err(c, "i2c_write: value didn't stick. 0x%04x = 0x%02x != 0x%02x", addr, actual, val);
	}
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}

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static void s5k3l6xx_i2c_write2(struct s5k3l6xx *state, u16 addr, u16 val)
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{
	struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
	u8 buf[4] = { addr >> 8, addr & 0xFF, (val >> 8) & 0xff, val & 0xff };

	struct i2c_msg msg[] = {
		{ .addr = c->addr, .flags = 0,
		  .len = 4, .buf = buf },
	};
	int ret;

	if (state->error)
		return;

	ret = i2c_transfer(c->adapter, msg, 1);

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	v4l2_dbg(3, debug, c, "i2c_write to 0x%04x : 0x%04x\n", addr, val);
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	if (ret != 1) {
		v4l2_err(c, "i2c_write: error during transfer (%d)\n", ret);
		state->error = ret;
	}
}

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static void s5k3l6xx_submit_regs(struct s5k3l6xx *state, const struct s5k3l6xx_reg *regs, u16 regcount) {
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       unsigned i;
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       for (i = 0; i < regcount; i++) {
	       if (regs[i].size == 2)
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		       s5k3l6xx_i2c_write2(state, regs[i].address, regs[i].val);
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	       else
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		       s5k3l6xx_i2c_write(state, regs[i].address, (u8)regs[i].val);
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       }
}

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static u8 s5k3l6xx_read(struct s5k3l6xx *state, u16 addr)
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{
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	return s5k3l6xx_i2c_read(state, addr);
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}

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static void s5k3l6xx_write(struct s5k3l6xx *state, u16 addr, u8 val)
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{
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	s5k3l6xx_i2c_write(state, addr, val);
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}

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static void s5k3l6xx_submit_regstable(struct s5k3l6xx *state, const struct regstable *regs)
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{
	struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
	unsigned i;
	for (i = 0; i < regs->entry_count; i++) {
		u16 addr = regs->entries[i].address;
		u8 val = regs->entries[i].value;
		if (debug >= 5) {
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			u8 res = __s5k3l6xx_i2c_read(state, addr);
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			if (res != val) {
				v4l2_dbg(5, debug, c, "overwriting: 0x%04x : 0x%02x\n", addr, res);
			}
		}
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		s5k3l6xx_i2c_write(state, addr, val);
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	}
}

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static int s5k3l6xx_find_pixfmt(const struct v4l2_mbus_framefmt *mf)
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{
	int i, c = -1;

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	for (i = 0; i < ARRAY_SIZE(s5k3l6xx_frames); i++) {
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		if ((mf->colorspace != V4L2_COLORSPACE_DEFAULT)
				&& (mf->colorspace != V4L2_COLORSPACE_RAW))
			continue;
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		if ((mf->width != s5k3l6xx_frames[i].width) || (mf->height != s5k3l6xx_frames[i].height))
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			continue;
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		if (mf->code == s5k3l6xx_frames[i].code)
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			return i;
	}
	return c;
}

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static int s5k3l6xx_clear_error(struct s5k3l6xx *state)
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{
	int ret = state->error;

	state->error = 0;
	return ret;
}

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static const struct s5k3l6xx_reg setstream[] = {
	{ S5K3L6XX_REG_DATA_FORMAT, S5K3L6XX_DATA_FORMAT_RAW8, 2 },
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	// Noise reduction
	// Bit 0x0080 will create noise when off (by default)
	// Raises data pedestal to 15-16.
	{ 0x307a, 0x0d00, 2 },
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};

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static void s5k3l6xx_hw_set_config(struct s5k3l6xx *state) {
	const struct s5k3l6xx_frame *frame_fmt = state->frame_fmt;
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	v4l2_dbg(3, debug, &state->sd, "Setting frame format %s", frame_fmt->name);
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	s5k3l6xx_submit_regs(state, frame_fmt->streamregs, frame_fmt->streamregcount);
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	// This may mess up PLL settings...
	// If the above already enabled streaming (setfile A), we're also in trouble.
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	s5k3l6xx_submit_regs(state, setstream, ARRAY_SIZE(setstream));
	s5k3l6xx_write(state, S5K3L6XX_REG_LANE_MODE, state->nlanes - 1);
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	s5k3l6xx_submit_regstable(state, &state->debug_regs);
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}

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static void s5k3l6xx_hw_set_test_pattern(struct s5k3l6xx *state, int id)
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{
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	s5k3l6xx_write(state, S5K3L6XX_REG_TEST_PATTERN_MODE, (u8)id);
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}


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static void s5k3l6xx_gpio_assert(struct s5k3l6xx *state, int id)
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{
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	struct s5k3l6xx_gpio *gpio = &state->gpios[id];
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	if (gpio == 0)
		return;

	gpio_set_value(gpio->gpio, gpio->level);
}

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static void s5k3l6xx_gpio_deassert(struct s5k3l6xx *state, int id)
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{
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	struct s5k3l6xx_gpio *gpio = &state->gpios[id];
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	if (gpio == 0)
		return;

	gpio_set_value(gpio->gpio, !gpio->level);
}

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static int s5k3l6xx_power_on(struct s5k3l6xx *state)
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{
	int ret;

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	ret = regulator_enable(state->supply);
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	if (ret < 0)
		goto err;

	ret = clk_set_rate(state->clock, state->mclk_frequency);
	if (ret < 0)
		goto err_reg_dis;

	ret = clk_prepare_enable(state->clock);
	if (ret < 0)
		goto err_reg_dis;

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	v4l2_dbg(1, debug, &state->sd, "ON. clock frequency: %ld\n",
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		 clk_get_rate(state->clock));

	usleep_range(50, 100);
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	s5k3l6xx_gpio_deassert(state, RST);
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	return 0;

err_reg_dis:
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	if (regulator_is_enabled(state->supply))
		regulator_disable(state->supply);
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err:
	v4l2_err(&state->sd, "%s() failed (%d)\n", __func__, ret);
	return ret;
}

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static int s5k3l6xx_power_off(struct s5k3l6xx *state)
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{
	int ret;

	state->streaming = 0;
	state->apply_cfg = 0;
	state->apply_crop = 0;

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	s5k3l6xx_gpio_assert(state, RST);
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	if (!IS_ERR(state->clock))
		clk_disable_unprepare(state->clock);

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	if (!regulator_is_enabled(state->supply))
		return 0;

	ret = regulator_disable(state->supply);
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	if (ret < 0)
		v4l2_err(&state->sd, "failed to disable regulators\n");
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	else
		v4l2_dbg(1, debug, &state->sd, "OFF\n");
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	return 0;
}

/*
 * V4L2 subdev core and video operations
 */

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static int s5k3l6xx_set_power(struct v4l2_subdev *sd, int on)
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{
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	struct s5k3l6xx *state = to_s5k3l6xx(sd);
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	int ret = 0;

	mutex_lock(&state->lock);

	if (state->power != !on)
		goto out;

	if (on) {
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		ret = s5k3l6xx_power_on(state); // TODO: test this
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		if (ret < 0)
			goto out;

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		ret = s5k3l6xx_clear_error(state);
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		if (!ret)
			state->power++;
	} else {
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		s5k3l6xx_power_off(state);
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		state->power--;
	}

out:
	mutex_unlock(&state->lock);
	return ret;
}

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static void s5k3l6xx_hw_set_stream(struct s5k3l6xx *state, int enable)
649
{
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	v4l2_dbg(3, debug, &state->sd, "set_stream %d", enable);
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	s5k3l6xx_i2c_write(state, S5K3L6XX_REG_MODE_SELECT, enable ? S5K3L6XX_MODE_STREAMING : S5K3L6XX_MODE_STANDBY);
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}

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static int s5k3l6xx_s_stream(struct v4l2_subdev *sd, int on)
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{
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	struct s5k3l6xx *state = to_s5k3l6xx(sd);
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	struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
	int ret = 0;

	if (state->streaming == !!on) {
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		return 0;
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	}

	if (on) {
		ret = pm_runtime_get_sync(&c->dev);
		if (ret < 0) {
			dev_err(&c->dev, "%s: pm_runtime_get failed: %d\n",
				__func__, ret);
			pm_runtime_put_noidle(&c->dev);
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			return ret;
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		}

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		ret = v4l2_ctrl_handler_setup(&state->ctrls.handler);
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		if (ret < 0)
			goto out;
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		mutex_lock(&state->lock);
		s5k3l6xx_hw_set_config(state);
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		s5k3l6xx_hw_set_stream(state, 1);
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	} else {
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		mutex_lock(&state->lock);
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		s5k3l6xx_hw_set_stream(state, 0);
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		pm_runtime_put(&c->dev);
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	}
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	ret = s5k3l6xx_clear_error(state);
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	if (!ret)
		state->streaming = !state->streaming;

out:
	mutex_unlock(&state->lock);

	return ret;
}

/*
 * V4L2 subdev pad level and video operations
 */
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static int s5k3l6xx_enum_mbus_code(struct v4l2_subdev *sd,
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				 struct v4l2_subdev_pad_config *cfg,
				 struct v4l2_subdev_mbus_code_enum *code)
{
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	if (code->index >= ARRAY_SIZE(s5k3l6xx_frames))
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		return -EINVAL;
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	code->code = s5k3l6xx_frames[code->index].code;
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	return 0;
}

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static int s5k3l6xx_enum_frame_size(struct v4l2_subdev *sd,
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				  struct v4l2_subdev_pad_config *cfg,
				  struct v4l2_subdev_frame_size_enum *fse)
{
	int i;

	if (fse->index > 0)
		return -EINVAL;

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	i = ARRAY_SIZE(s5k3l6xx_frames);
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	while (--i)
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		if (fse->code == s5k3l6xx_frames[i].code)
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			break;
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	fse->code = s5k3l6xx_frames[i].code;
	fse->min_width = s5k3l6xx_frames[i].width;
	fse->max_width = s5k3l6xx_frames[i].width;
	fse->max_height = s5k3l6xx_frames[i].height;
	fse->min_height = s5k3l6xx_frames[i].height;
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	return 0;
}

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static int s5k3l6xx_try_cis_format(struct v4l2_mbus_framefmt *mf)
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{
	int pixfmt;
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	const struct s5k3l6xx_frame *mode = v4l2_find_nearest_size(s5k3l6xx_frames,
				      ARRAY_SIZE(s5k3l6xx_frames),
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				      width, height,
				      mf->width, mf->height);
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	struct v4l2_mbus_framefmt candidate = *mf;
	candidate.width = mode->width;
	candidate.height = mode->height;
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	pixfmt = s5k3l6xx_find_pixfmt(&candidate);
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	if (pixfmt < 0)
		return pixfmt;

	mf->colorspace = V4L2_COLORSPACE_RAW;
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	mf->code = s5k3l6xx_frames[pixfmt].code;
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	mf->field = V4L2_FIELD_NONE;

	return pixfmt;
}

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static int s5k3l6xx_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
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			  struct v4l2_subdev_format *fmt)
{
	struct v4l2_mbus_framefmt *mf;

	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
		mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
		fmt->format = *mf;
		return 0;
	}

	mf = &fmt->format;
	if (fmt->pad == PAD_CIS) {
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		s5k3l6xx_try_cis_format(mf);
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		return 0;
	}
	return 0;
}

771
static int s5k3l6xx_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
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			  struct v4l2_subdev_format *fmt)
{
	struct v4l2_mbus_framefmt *mf = &fmt->format;
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	struct s5k3l6xx *state = to_s5k3l6xx(sd);
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	int pixfmt_idx = 0;
	mf->field = V4L2_FIELD_NONE;

	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
		*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = *mf;
		return 0;
	}

	mutex_lock(&state->lock);

	if (state->streaming) {
		mutex_unlock(&state->lock);
		return -EBUSY;
	}

791
	if (state->debug_frame) {
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		state->frame_fmt = &s5k3l6xx_frame_debug;
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		// Keep frame width/height as requested.
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	} else {
795
		pixfmt_idx = s5k3l6xx_try_cis_format(mf);
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		if (pixfmt_idx == -1) {
			v4l2_err(sd, "set_fmt choice unsupported");
			mutex_unlock(&state->lock);
			return -EINVAL; // could not find the format. Unsupported
		}
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		state->frame_fmt = &s5k3l6xx_frames[pixfmt_idx];
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		mf->width = state->frame_fmt->width;
		mf->height = state->frame_fmt->height;
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	}
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806
	mf->code = state->frame_fmt->code;
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	mf->colorspace = V4L2_COLORSPACE_RAW;

	mutex_unlock(&state->lock);
	return 0;
}

enum selection_rect { R_CIS, R_CROP_SINK, R_COMPOSE, R_CROP_SOURCE, R_INVALID };

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static const struct v4l2_subdev_pad_ops s5k3l6xx_cis_pad_ops = {
	.enum_mbus_code		= s5k3l6xx_enum_mbus_code,
	.enum_frame_size	= s5k3l6xx_enum_frame_size,
	.get_fmt		= s5k3l6xx_get_fmt,
	.set_fmt		= s5k3l6xx_set_fmt,
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};

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static const struct v4l2_subdev_pad_ops s5k3l6xx_pad_ops = {
	.enum_mbus_code		= s5k3l6xx_enum_mbus_code,
	.enum_frame_size	= s5k3l6xx_enum_frame_size,
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//	.enum_frame_interval	= s5k5baf_enum_frame_interval,
	// doesn't seem to be used... ioctl(3, VIDIOC_S_FMT, ...)
	// instead seems to call enum_fmt, which does enum_mbus_code here.
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	.get_fmt		= s5k3l6xx_get_fmt,
	.set_fmt		= s5k3l6xx_set_fmt,
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};

832
static const struct v4l2_subdev_video_ops s5k3l6xx_video_ops = {
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	//.g_frame_interval	= s5k5baf_g_frame_interval,
	//.s_frame_interval	= s5k5baf_s_frame_interval,
835
	.s_stream		= s5k3l6xx_s_stream,
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};

/*
 * V4L2 subdev controls
 */

842
static int s5k3l6xx_s_ctrl(struct v4l2_ctrl *ctrl)
843 844
{
	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
845
	struct s5k3l6xx *state = to_s5k3l6xx(sd);
846
	struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
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	int in_use;
	int ret = 0;
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	v4l2_dbg(1, debug, sd, "ctrl: %s, value: %d\n", ctrl->name, ctrl->val);

	mutex_lock(&state->lock);

854 855
	// Don't do anything when powered off.
	// It will get called again when powering up.
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	if (state->power == 0)
		goto unlock;
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	/* v4l2_ctrl_handler_setup() function may not be used in the device’s runtime PM
	 * runtime_resume callback, as it has no way to figure out the power state of the device.
	 * https://www.kernel.org/doc/html/latest/driver-api/media/camera-sensor.html#control-framework
	 * Okay, so what's the right way to do it? So far relying on state->power.
	 */

	in_use = pm_runtime_get_if_in_use(&c->dev);
865

866
	switch (ctrl->id) {
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	case V4L2_CID_ANALOGUE_GAIN:
		// Analog gain supported up to 0x200 (16). Gain = register / 32, so 0x20 gives gain 1.
869
		s5k3l6xx_i2c_write2(state, S5K3L6XX_REG_ANALOG_GAIN, (u16)ctrl->val & 0x3ff);
870
		break;
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	case V4L2_CID_DIGITAL_GAIN:
		s5k3l6xx_i2c_write2(state, S5K3L6XX_REG_DIGITAL_GAIN, (u16)ctrl->val & 0xfff);
		break;
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	case V4L2_CID_EXPOSURE:
		s5k3l6xx_i2c_write2(state, S5K3L6XX_REG_COARSE_INTEGRATION_TIME, (u16)ctrl->val);
		break;
877
	case V4L2_CID_TEST_PATTERN:
878
		state->apply_test_solid = (ctrl->val == S5K3L6XX_TEST_PATTERN_SOLID_COLOR);
879
		v4l2_dbg(3, debug, sd, "Setting pattern %d", ctrl->val);
880
		s5k3l6xx_hw_set_test_pattern(state, ctrl->val);
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		break;
	case V4L2_CID_TEST_PATTERN_RED:
883
		s5k3l6xx_i2c_write2(state, S5K3L6XX_REG_TEST_DATA_RED, (u16)ctrl->val & 0x3ff);
884
		if (state->apply_test_solid)
885
			s5k3l6xx_hw_set_test_pattern(state, S5K3L6XX_TEST_PATTERN_SOLID_COLOR);
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		break;
	case V4L2_CID_TEST_PATTERN_GREENR:
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		s5k3l6xx_i2c_write2(state, S5K3L6XX_REG_TEST_DATA_GREENR, (u16)ctrl->val & 0x3ff);
889
		if (state->apply_test_solid)
890
			s5k3l6xx_hw_set_test_pattern(state, S5K3L6XX_TEST_PATTERN_SOLID_COLOR);
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		break;
	case V4L2_CID_TEST_PATTERN_BLUE:
893
		s5k3l6xx_i2c_write2(state, S5K3L6XX_REG_TEST_DATA_BLUE, (u16)ctrl->val & 0x3ff);
894
		if (state->apply_test_solid)
895
			s5k3l6xx_hw_set_test_pattern(state, S5K3L6XX_TEST_PATTERN_SOLID_COLOR);
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		break;
	case V4L2_CID_TEST_PATTERN_GREENB:
898
		s5k3l6xx_i2c_write2(state, S5K3L6XX_REG_TEST_DATA_GREENB, (u16)ctrl->val & 0x3ff);
899
		if (state->apply_test_solid)
900
			s5k3l6xx_hw_set_test_pattern(state, S5K3L6XX_TEST_PATTERN_SOLID_COLOR);
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		break;
	}
903
	ret = s5k3l6xx_clear_error(state);
904

905
	if (in_use) { // came from other context than resume, need to manage PM
906
		pm_runtime_put(&c->dev);
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	}
unlock:
909 910 911 912
	mutex_unlock(&state->lock);
	return ret;
}

913 914
static const struct v4l2_ctrl_ops s5k3l6xx_ctrl_ops = {
	.s_ctrl	= s5k3l6xx_s_ctrl,
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};

static const char * const s5k3l6_test_pattern_menu[] = {
	"Disabled",
	"Solid", // Color selectable
	"Bars", // 8 bars 100% saturation: black, blue, red, magents, green, cyan, yellow, white
	"Fade", // Bars fading towards 50% at the bottom. 512px high. Subdivided into left smooth and right quantized halves.
	"White",
	"PN9", // pseudo-random noise
	"LFSR32",
	"Address",
};

928
static int s5k3l6xx_initialize_ctrls(struct s5k3l6xx *state)
929
{
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	const struct v4l2_ctrl_ops *ops = &s5k3l6xx_ctrl_ops;
	struct s5k3l6xx_ctrls *ctrls = &state->ctrls;
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	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
	int ret;

	ret = v4l2_ctrl_handler_init(hdl, 16);
	if (ret < 0) {
		v4l2_err(&state->sd, "cannot init ctrl handler (%d)\n", ret);
		return ret;
	}

941
	// Exposure time (min: 2; max: frame length lines - 2; default: reset value)
942
	ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
943 944
					    2, 3118, 1, 0x03de);

945 946
	// Total gain: 32 <=> 1x
	ctrls->analog_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
947
					0x20, 0x200, 1, 0x20);
948

949
	// Digital gain range: 1.0x - 3.0x
950
	ctrls->digital_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_DIGITAL_GAIN,
951
					0x100, 0x300, 1, 0x100);
952

953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976
	v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
				     ARRAY_SIZE(s5k3l6_test_pattern_menu) - 1,
				     0, 0, s5k3l6_test_pattern_menu);

	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_TEST_PATTERN_RED, 0, 1023, 1, 512);
	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_TEST_PATTERN_GREENR, 0, 1023, 1, 512);
	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_TEST_PATTERN_BLUE, 0, 1023, 1, 512);
	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_TEST_PATTERN_GREENB, 0, 1023, 1, 512);

	if (hdl->error) {
		v4l2_err(&state->sd, "error creating controls (%d)\n",
			 hdl->error);
		ret = hdl->error;
		v4l2_ctrl_handler_free(hdl);
		return ret;
	}

	state->sd.ctrl_handler = hdl;
	return 0;
}

/*
 * V4L2 subdev internal operations
 */
977
static int s5k3l6xx_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
978 979 980 981
{
	struct v4l2_mbus_framefmt *mf;

	mf = v4l2_subdev_get_try_format(sd, fh->pad, PAD_CIS);
982
	s5k3l6xx_try_cis_format(mf);
983 984 985 986
	return 0;
}

static const struct v4l2_subdev_ops s5k5baf_cis_subdev_ops = {
987
	.pad	= &s5k3l6xx_cis_pad_ops,
988 989 990
};

static const struct v4l2_subdev_internal_ops s5k5baf_cis_subdev_internal_ops = {