Commit 1c21a978 authored by Daniel Baluta's avatar Daniel Baluta Committed by Angus Ainslie (Purism)
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ASoC: fsl_sai: Set SAI Channel Mode to Output Mode



From SAI datasheet:

CHMOD, configures if transmit data pins are configured for TDM mode
or Output mode.
	* (0) TDM mode, transmit data pins are tri-stated when slots are
	masked or channels are disabled.
	* (1) Output mode, transmit data pins are never tri-stated and
	will output zero when slots are masked or channels are disabled.

When data pins are tri-stated, there is noise on some channels
when FS clock value is high and data is read while fsclk is
transitioning from high to low.

Fix this by setting CHMOD to Output Mode so that pins will output zero
when slots are masked or channels are disabled.

Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: default avatarCosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Signed-off-by: default avatarDaniel Baluta <daniel.baluta@nxp.com>
parent 92b7616f
Pipeline #35075 passed with stage
in 25 minutes and 6 seconds
......@@ -524,6 +524,12 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
/*
* set CHMOD to Output Mode so that transmit data pins will
* output zero when slots are masked or channels are disabled
*/
val_cr4 |= FSL_SAI_CR4_CHMOD;
/*
* For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
* generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
......@@ -534,14 +540,16 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
if (!sai->slave_mode[tx]) {
if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
regmap_update_bits(sai->regmap, FSL_SAI_TCR4(offset),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
FSL_SAI_CR4_CHMOD_MASK,
val_cr4);
regmap_update_bits(sai->regmap, FSL_SAI_TCR5(offset),
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
FSL_SAI_CR5_FBT_MASK, val_cr5);
} else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
regmap_update_bits(sai->regmap, FSL_SAI_RCR4(offset),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
FSL_SAI_CR4_CHMOD_MASK,
val_cr4);
regmap_update_bits(sai->regmap, FSL_SAI_RCR5(offset),
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
......@@ -559,7 +567,8 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
}
regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
FSL_SAI_CR4_CHMOD_MASK,
val_cr4);
regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, offset),
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
......
......@@ -108,6 +108,8 @@
#define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
#define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
#define FSL_SAI_CR4_SYWD_MASK (0x1f << 8)
#define FSL_SAI_CR4_CHMOD BIT(5)
#define FSL_SAI_CR4_CHMOD_MASK GENMASK(5, 5)
#define FSL_SAI_CR4_MF BIT(4)
#define FSL_SAI_CR4_FSE BIT(3)
#define FSL_SAI_CR4_FSP BIT(1)
......
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