Commit 3a379bbc authored by Boris Brezillon's avatar Boris Brezillon

i3c: Add core I3C infrastructure

Add core infrastructure to support I3C in Linux and document it.

This infrastructure adds basic I3C support. Advanced features will be
added afterwards.

There are a few design choices that are worth mentioning because they
impact the way I3C device drivers can interact with their devices:

- all functions used to send I3C/I2C frames must be called in
  non-atomic context. Mainly done this way to ease implementation, but
  this is not set in stone, and if anyone needs async support, new
  functions can be added later on.
- the bus element is a separate object, but it's tightly coupled with
  the master object. We thus have a 1:1 relationship between i3c_bus
  and i3c_master_controller objects, and if 2 master controllers are
  connected to the same bus and both exposed to the same Linux instance
  they will appear as two distinct busses, and devices on this bus will
  be exposed twice.
- I2C backward compatibility has been designed to be transparent to I2C
  drivers and the I2C subsystem. The I3C master just registers an I2C
  adapter which creates a new I2C bus. I'd say that, from a
  representation PoV it's not ideal because what should appear as a
  single I3C bus exposing I3C and I2C devices here appears as 2
  different buses connected to each other through the parenting (the
  I3C master is the parent of the I2C and I3C busses).
  On the other hand, I don't see a better solution if we want something
  that is not invasive.

Missing features:
- I3C HDR modes are not supported
- no support for multi-master and the associated concepts (mastership
  handover, support for secondary masters, ...)
- I2C devices can only be described using DT because this is the only
  use case I have. However, the framework can easily be extended with
  ACPI and board info support
- I3C slave framework. This has been completely omitted, but shouldn't
  have a huge impact on the I3C framework because I3C slaves don't see
  the whole bus, it's only about handling master requests and generating
  IBIs. Some of the struct, constant and enum definitions could be
  shared, but most of the I3C slave framework logic will be different
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 65102238
......@@ -57,6 +57,8 @@ source "drivers/char/Kconfig"
source "drivers/i2c/Kconfig"
source "drivers/i3c/Kconfig"
source "drivers/spi/Kconfig"
source "drivers/spmi/Kconfig"
......
......@@ -111,7 +111,7 @@ obj-$(CONFIG_SERIO) += input/serio/
obj-$(CONFIG_GAMEPORT) += input/gameport/
obj-$(CONFIG_INPUT) += input/
obj-$(CONFIG_RTC_LIB) += rtc/
obj-y += i2c/ media/
obj-y += i2c/ i3c/ media/
obj-$(CONFIG_PPS) += pps/
obj-y += ptp/
obj-$(CONFIG_W1) += w1/
......
# SPDX-License-Identifier: GPL-2.0
menuconfig I3C
tristate "I3C support"
select I2C
help
I3C is a serial protocol standardized by the MIPI alliance.
It's supposed to be backward compatible with I2C while providing
support for high speed transfers and native interrupt support
without the need for extra pins.
The I3C protocol also standardizes the slave device types and is
mainly designed to communicate with sensors.
If you want I3C support, you should say Y here and also to the
specific driver for your bus adapter(s) below.
This I3C support can also be built as a module. If so, the module
will be called i3c.
if I3C
source "drivers/i3c/master/Kconfig"
endif # I3C
# SPDX-License-Identifier: GPL-2.0
i3c-y := device.o master.o
obj-$(CONFIG_I3C) += i3c.o
obj-$(CONFIG_I3C) += master/
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Cadence Design Systems Inc.
*
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
*/
#include <linux/atomic.h>
#include <linux/bug.h>
#include <linux/completion.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include "internals.h"
/**
* i3c_device_do_priv_xfers() - do I3C SDR private transfers directed to a
* specific device
*
* @dev: device with which the transfers should be done
* @xfers: array of transfers
* @nxfers: number of transfers
*
* Initiate one or several private SDR transfers with @dev.
*
* This function can sleep and thus cannot be called in atomic context.
*
* Return: 0 in case of success, a negative error core otherwise.
*/
int i3c_device_do_priv_xfers(struct i3c_device *dev,
struct i3c_priv_xfer *xfers,
int nxfers)
{
int ret, i;
if (nxfers < 1)
return 0;
for (i = 0; i < nxfers; i++) {
if (!xfers[i].len || !xfers[i].data.in)
return -EINVAL;
}
i3c_bus_normaluse_lock(dev->bus);
ret = i3c_dev_do_priv_xfers_locked(dev->desc, xfers, nxfers);
i3c_bus_normaluse_unlock(dev->bus);
return ret;
}
EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);
/**
* i3c_device_get_info() - get I3C device information
*
* @dev: device we want information on
* @info: the information object to fill in
*
* Retrieve I3C dev info.
*/
void i3c_device_get_info(struct i3c_device *dev,
struct i3c_device_info *info)
{
if (!info)
return;
i3c_bus_normaluse_lock(dev->bus);
if (dev->desc)
*info = dev->desc->info;
i3c_bus_normaluse_unlock(dev->bus);
}
EXPORT_SYMBOL_GPL(i3c_device_get_info);
/**
* i3c_device_disable_ibi() - Disable IBIs coming from a specific device
* @dev: device on which IBIs should be disabled
*
* This function disable IBIs coming from a specific device and wait for
* all pending IBIs to be processed.
*
* Return: 0 in case of success, a negative error core otherwise.
*/
int i3c_device_disable_ibi(struct i3c_device *dev)
{
int ret = -ENOENT;
i3c_bus_normaluse_lock(dev->bus);
if (dev->desc) {
mutex_lock(&dev->desc->ibi_lock);
ret = i3c_dev_disable_ibi_locked(dev->desc);
mutex_unlock(&dev->desc->ibi_lock);
}
i3c_bus_normaluse_unlock(dev->bus);
return ret;
}
EXPORT_SYMBOL_GPL(i3c_device_disable_ibi);
/**
* i3c_device_enable_ibi() - Enable IBIs coming from a specific device
* @dev: device on which IBIs should be enabled
*
* This function enable IBIs coming from a specific device and wait for
* all pending IBIs to be processed. This should be called on a device
* where i3c_device_request_ibi() has succeeded.
*
* Note that IBIs from this device might be received before this function
* returns to its caller.
*
* Return: 0 in case of success, a negative error core otherwise.
*/
int i3c_device_enable_ibi(struct i3c_device *dev)
{
int ret = -ENOENT;
i3c_bus_normaluse_lock(dev->bus);
if (dev->desc) {
mutex_lock(&dev->desc->ibi_lock);
ret = i3c_dev_enable_ibi_locked(dev->desc);
mutex_unlock(&dev->desc->ibi_lock);
}
i3c_bus_normaluse_unlock(dev->bus);
return ret;
}
EXPORT_SYMBOL_GPL(i3c_device_enable_ibi);
/**
* i3c_device_request_ibi() - Request an IBI
* @dev: device for which we should enable IBIs
* @req: setup requested for this IBI
*
* This function is responsible for pre-allocating all resources needed to
* process IBIs coming from @dev. When this function returns, the IBI is not
* enabled until i3c_device_enable_ibi() is called.
*
* Return: 0 in case of success, a negative error core otherwise.
*/
int i3c_device_request_ibi(struct i3c_device *dev,
const struct i3c_ibi_setup *req)
{
int ret = -ENOENT;
if (!req->handler || !req->num_slots)
return -EINVAL;
i3c_bus_normaluse_lock(dev->bus);
if (dev->desc) {
mutex_lock(&dev->desc->ibi_lock);
ret = i3c_dev_request_ibi_locked(dev->desc, req);
mutex_unlock(&dev->desc->ibi_lock);
}
i3c_bus_normaluse_unlock(dev->bus);
return ret;
}
EXPORT_SYMBOL_GPL(i3c_device_request_ibi);
/**
* i3c_device_free_ibi() - Free all resources needed for IBI handling
* @dev: device on which you want to release IBI resources
*
* This function is responsible for de-allocating resources previously
* allocated by i3c_device_request_ibi(). It should be called after disabling
* IBIs with i3c_device_disable_ibi().
*/
void i3c_device_free_ibi(struct i3c_device *dev)
{
i3c_bus_normaluse_lock(dev->bus);
if (dev->desc) {
mutex_lock(&dev->desc->ibi_lock);
i3c_dev_free_ibi_locked(dev->desc);
mutex_unlock(&dev->desc->ibi_lock);
}
i3c_bus_normaluse_unlock(dev->bus);
}
EXPORT_SYMBOL_GPL(i3c_device_free_ibi);
/**
* i3cdev_to_dev() - Returns the device embedded in @i3cdev
* @i3cdev: I3C device
*
* Return: a pointer to a device object.
*/
struct device *i3cdev_to_dev(struct i3c_device *i3cdev)
{
return &i3cdev->dev;
}
EXPORT_SYMBOL_GPL(i3cdev_to_dev);
/**
* dev_to_i3cdev() - Returns the I3C device containing @dev
* @dev: device object
*
* Return: a pointer to an I3C device object.
*/
struct i3c_device *dev_to_i3cdev(struct device *dev)
{
return container_of(dev, struct i3c_device, dev);
}
EXPORT_SYMBOL_GPL(dev_to_i3cdev);
/**
* i3c_driver_register_with_owner() - register an I3C device driver
*
* @drv: driver to register
* @owner: module that owns this driver
*
* Register @drv to the core.
*
* Return: 0 in case of success, a negative error core otherwise.
*/
int i3c_driver_register_with_owner(struct i3c_driver *drv, struct module *owner)
{
drv->driver.owner = owner;
drv->driver.bus = &i3c_bus_type;
return driver_register(&drv->driver);
}
EXPORT_SYMBOL_GPL(i3c_driver_register_with_owner);
/**
* i3c_driver_unregister() - unregister an I3C device driver
*
* @drv: driver to unregister
*
* Unregister @drv.
*/
void i3c_driver_unregister(struct i3c_driver *drv)
{
driver_unregister(&drv->driver);
}
EXPORT_SYMBOL_GPL(i3c_driver_unregister);
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Cadence Design Systems Inc.
*
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
*/
#ifndef I3C_INTERNALS_H
#define I3C_INTERNALS_H
#include <linux/i3c/master.h>
extern struct bus_type i3c_bus_type;
void i3c_bus_normaluse_lock(struct i3c_bus *bus);
void i3c_bus_normaluse_unlock(struct i3c_bus *bus);
int i3c_dev_do_priv_xfers_locked(struct i3c_dev_desc *dev,
struct i3c_priv_xfer *xfers,
int nxfers);
int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev);
int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev);
int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev,
const struct i3c_ibi_setup *req);
void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev);
#endif /* I3C_INTERNAL_H */
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Cadence Design Systems Inc.
*
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
*/
#ifndef I3C_CCC_H
#define I3C_CCC_H
#include <linux/bitops.h>
#include <linux/i3c/device.h>
/* I3C CCC (Common Command Codes) related definitions */
#define I3C_CCC_DIRECT BIT(7)
#define I3C_CCC_ID(id, broadcast) \
((id) | ((broadcast) ? 0 : I3C_CCC_DIRECT))
/* Commands valid in both broadcast and unicast modes */
#define I3C_CCC_ENEC(broadcast) I3C_CCC_ID(0x0, broadcast)
#define I3C_CCC_DISEC(broadcast) I3C_CCC_ID(0x1, broadcast)
#define I3C_CCC_ENTAS(as, broadcast) I3C_CCC_ID(0x2 + (as), broadcast)
#define I3C_CCC_RSTDAA(broadcast) I3C_CCC_ID(0x6, broadcast)
#define I3C_CCC_SETMWL(broadcast) I3C_CCC_ID(0x9, broadcast)
#define I3C_CCC_SETMRL(broadcast) I3C_CCC_ID(0xa, broadcast)
#define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28 : 0x98)
#define I3C_CCC_VENDOR(id, broadcast) ((id) + ((broadcast) ? 0x61 : 0xe0))
/* Broadcast-only commands */
#define I3C_CCC_ENTDAA I3C_CCC_ID(0x7, true)
#define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true)
#define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true)
#define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true)
/* Unicast-only commands */
#define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false)
#define I3C_CCC_SETNEWDA I3C_CCC_ID(0x8, false)
#define I3C_CCC_GETMWL I3C_CCC_ID(0xb, false)
#define I3C_CCC_GETMRL I3C_CCC_ID(0xc, false)
#define I3C_CCC_GETPID I3C_CCC_ID(0xd, false)
#define I3C_CCC_GETBCR I3C_CCC_ID(0xe, false)
#define I3C_CCC_GETDCR I3C_CCC_ID(0xf, false)
#define I3C_CCC_GETSTATUS I3C_CCC_ID(0x10, false)
#define I3C_CCC_GETACCMST I3C_CCC_ID(0x11, false)
#define I3C_CCC_SETBRGTGT I3C_CCC_ID(0x13, false)
#define I3C_CCC_GETMXDS I3C_CCC_ID(0x14, false)
#define I3C_CCC_GETHDRCAP I3C_CCC_ID(0x15, false)
#define I3C_CCC_GETXTIME I3C_CCC_ID(0x19, false)
#define I3C_CCC_EVENT_SIR BIT(0)
#define I3C_CCC_EVENT_MR BIT(1)
#define I3C_CCC_EVENT_HJ BIT(3)
/**
* struct i3c_ccc_events - payload passed to ENEC/DISEC CCC
*
* @events: bitmask of I3C_CCC_EVENT_xxx events.
*
* Depending on the CCC command, the specific events coming from all devices
* (broadcast version) or a specific device (unicast version) will be
* enabled (ENEC) or disabled (DISEC).
*/
struct i3c_ccc_events {
u8 events;
};
/**
* struct i3c_ccc_mwl - payload passed to SETMWL/GETMWL CCC
*
* @len: maximum write length in bytes
*
* The maximum write length is only applicable to SDR private messages or
* extended Write CCCs (like SETXTIME).
*/
struct i3c_ccc_mwl {
__be16 len;
};
/**
* struct i3c_ccc_mrl - payload passed to SETMRL/GETMRL CCC
*
* @len: maximum read length in bytes
* @ibi_len: maximum IBI payload length
*
* The maximum read length is only applicable to SDR private messages or
* extended Read CCCs (like GETXTIME).
* The IBI length is only valid if the I3C slave is IBI capable
* (%I3C_BCR_IBI_REQ_CAP is set).
*/
struct i3c_ccc_mrl {
__be16 read_len;
u8 ibi_len;
} __packed;
/**
* struct i3c_ccc_dev_desc - I3C/I2C device descriptor used for DEFSLVS
*
* @dyn_addr: dynamic address assigned to the I3C slave or 0 if the entry is
* describing an I2C slave.
* @dcr: DCR value (not applicable to entries describing I2C devices)
* @lvr: LVR value (not applicable to entries describing I3C devices)
* @bcr: BCR value or 0 if this entry is describing an I2C slave
* @static_addr: static address or 0 if the device does not have a static
* address
*
* The DEFSLVS command should be passed an array of i3c_ccc_dev_desc
* descriptors (one entry per I3C/I2C dev controlled by the master).
*/
struct i3c_ccc_dev_desc {
u8 dyn_addr;
union {
u8 dcr;
u8 lvr;
};
u8 bcr;
u8 static_addr;
};
/**
* struct i3c_ccc_defslvs - payload passed to DEFSLVS CCC
*
* @count: number of dev descriptors
* @master: descriptor describing the current master
* @slaves: array of descriptors describing slaves controlled by the
* current master
*
* Information passed to the broadcast DEFSLVS to propagate device
* information to all masters currently acting as slaves on the bus.
* This is only meaningful if you have more than one master.
*/
struct i3c_ccc_defslvs {
u8 count;
struct i3c_ccc_dev_desc master;
struct i3c_ccc_dev_desc slaves[0];
} __packed;
/**
* enum i3c_ccc_test_mode - enum listing all available test modes
*
* @I3C_CCC_EXIT_TEST_MODE: exit test mode
* @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode
*/
enum i3c_ccc_test_mode {
I3C_CCC_EXIT_TEST_MODE,
I3C_CCC_VENDOR_TEST_MODE,
};
/**
* struct i3c_ccc_enttm - payload passed to ENTTM CCC
*
* @mode: one of the &enum i3c_ccc_test_mode modes
*
* Information passed to the ENTTM CCC to instruct an I3C device to enter a
* specific test mode.
*/
struct i3c_ccc_enttm {
u8 mode;
};
/**
* struct i3c_ccc_setda - payload passed to SETNEWDA and SETDASA CCCs
*
* @addr: dynamic address to assign to an I3C device
*
* Information passed to the SETNEWDA and SETDASA CCCs to assign/change the
* dynamic address of an I3C device.
*/
struct i3c_ccc_setda {
u8 addr;
};
/**
* struct i3c_ccc_getpid - payload passed to GETPID CCC
*
* @pid: 48 bits PID in big endian
*/
struct i3c_ccc_getpid {
u8 pid[6];
};
/**
* struct i3c_ccc_getbcr - payload passed to GETBCR CCC
*
* @bcr: BCR (Bus Characteristic Register) value
*/
struct i3c_ccc_getbcr {
u8 bcr;
};
/**
* struct i3c_ccc_getdcr - payload passed to GETDCR CCC
*
* @dcr: DCR (Device Characteristic Register) value
*/
struct i3c_ccc_getdcr {
u8 dcr;
};
#define I3C_CCC_STATUS_PENDING_INT(status) ((status) & GENMASK(3, 0))
#define I3C_CCC_STATUS_PROTOCOL_ERROR BIT(5)
#define I3C_CCC_STATUS_ACTIVITY_MODE(status) \
(((status) & GENMASK(7, 6)) >> 6)
/**
* struct i3c_ccc_getstatus - payload passed to GETSTATUS CCC
*
* @status: status of the I3C slave (see I3C_CCC_STATUS_xxx macros for more
* information).
*/
struct i3c_ccc_getstatus {
__be16 status;
};
/**
* struct i3c_ccc_getaccmst - payload passed to GETACCMST CCC
*
* @newmaster: address of the master taking bus ownership
*/
struct i3c_ccc_getaccmst {
u8 newmaster;
};
/**
* struct i3c_ccc_bridged_slave_desc - bridged slave descriptor
*
* @addr: dynamic address of the bridged device
* @id: ID of the slave device behind the bridge
*/
struct i3c_ccc_bridged_slave_desc {
u8 addr;
__be16 id;
} __packed;
/**
* struct i3c_ccc_setbrgtgt - payload passed to SETBRGTGT CCC
*
* @count: number of bridged slaves
* @bslaves: bridged slave descriptors
*/
struct i3c_ccc_setbrgtgt {
u8 count;
struct i3c_ccc_bridged_slave_desc bslaves[0];
} __packed;
/**
* enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
*/
enum i3c_sdr_max_data_rate {
I3C_SDR0_FSCL_MAX,
I3C_SDR1_FSCL_8MHZ,
I3C_SDR2_FSCL_6MHZ,
I3C_SDR3_FSCL_4MHZ,
I3C_SDR4_FSCL_2MHZ,
};
/**
* enum i3c_tsco - clock to data turn-around
*/
enum i3c_tsco {
I3C_TSCO_8NS,
I3C_TSCO_9NS,
I3C_TSCO_10NS,
I3C_TSCO_11NS,
I3C_TSCO_12NS,
};
#define I3C_CCC_MAX_SDR_FSCL_MASK GENMASK(2, 0)
#define I3C_CCC_MAX_SDR_FSCL(x) ((x) & I3C_CCC_MAX_SDR_FSCL_MASK)
/**
* struct i3c_ccc_getmxds - payload passed to GETMXDS CCC
*
* @maxwr: write limitations
* @maxrd: read limitations
* @maxrdturn: maximum read turn-around expressed micro-seconds and
* little-endian formatted
*/
struct i3c_ccc_getmxds {
u8 maxwr;
u8 maxrd;
u8 maxrdturn[3];
} __packed;
#define I3C_CCC_HDR_MODE(mode) BIT(mode)
/**
* struct i3c_ccc_gethdrcap - payload passed to GETHDRCAP CCC
*
* @modes: bitmap of supported HDR modes
*/
struct i3c_ccc_gethdrcap {
u8 modes;
} __packed;
/**
* enum i3c_ccc_setxtime_subcmd - SETXTIME sub-commands
*/
enum i3c_ccc_setxtime_subcmd {
I3C_CCC_SETXTIME_ST = 0x7f,
I3C_CCC_SETXTIME_DT = 0xbf,
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE0 = 0xdf,
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE1 = 0xef,
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE2 = 0xf7,
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE3 = 0xfb,
I3C_CCC_SETXTIME_ASYNC_TRIGGER = 0xfd,
I3C_CCC_SETXTIME_TPH = 0x3f,
I3C_CCC_SETXTIME_TU = 0x9f,
I3C_CCC_SETXTIME_ODR = 0x8f,
};
/**
* struct i3c_ccc_setxtime - payload passed to SETXTIME CCC
*
* @subcmd: one of the sub-commands ddefined in &enum i3c_ccc_setxtime_subcmd
* @data: sub-command payload. Amount of data is determined by
* &i3c_ccc_setxtime->subcmd
*/
struct i3c_ccc_setxtime {
u8 subcmd;
u8 data[0];