Commit 92c29b29 authored by Guido Gunther's avatar Guido Gunther Committed by Angus Ainslie (Purism)

imx8mq: dts: Add NWL dsi controller and Mixel dphy

Signed-off-by: Guido Gunther's avatarGuido Günther <guido.gunther@puri.sm>
parent 27530018
......@@ -745,6 +745,47 @@ sai2: sai@308b0000 {
status = "disabled";
};
mipi_dsi: mipi_dsi@30a00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mq-nwl-dsi";
reg = <0x30a00000 0x300>;
clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
<&clk IMX8MQ_CLK_DSI_AHB>,
<&clk IMX8MQ_CLK_DSI_IPG_DIV>,
<&clk IMX8MQ_CLK_DSI_PHY_REF>;
clock-names = "core", "rx_esc", "tx_esc", "phy_ref";
assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
<&clk IMX8MQ_CLK_DSI_CORE>,
<&clk IMX8MQ_CLK_DSI_IPG_DIV>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
<&clk IMX8MQ_SYS1_PLL_266M>;
assigned-clock-rates = <80000000>,
<266000000>,
<20000000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pgc_mipi>;
src = <&src>;
mux-sel = <&iomuxc_gpr>;
phys = <&dphy>;
phy-names = "dphy";
status = "disabled";
};
dphy: dphy@30a00300 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mq-mipi-dphy";
reg = <0x30a00300 0x100>;
clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
clock-names = "phy_ref";
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <24000000>;
#phy-cells = <0>;
status = "disabled";
};
i2c1: i2c@30a20000 {
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
reg = <0x30a20000 0x10000>;
......
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