Commit fa33eba9 authored by Daniel Baluta's avatar Daniel Baluta Committed by Angus Ainslie (Purism)

ASoC: fsl_sai: Add support to enable multiple data lines

SAI supports up to 8 Rx/Tx data lines which can be enabled
using TCE/RCE bits of TCR3/RCR3 registers.

Data lines to be enabled are read from DT fsl,dl_mask property.
By default (if no DT entry is provided) only data line 0 is enabled.

Note:
We can only enable consecutive data lines starting with data line #0.
Signed-off-by: default avatarDaniel Baluta <daniel.baluta@nxp.com>
parent fea4a547
......@@ -601,7 +601,7 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
FSL_SAI_CR3_TRCE_MASK,
FSL_SAI_CR3_TRCE);
FSL_SAI_CR3_TRCE(sai->soc_data->dl_mask[tx]);
ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
......@@ -887,6 +887,14 @@ static int fsl_sai_probe(struct platform_device *pdev)
}
}
/* active data lines mask for TX/RX, defaults to 1 (only the first
* data line is enabled
*/
sai->dl_mask[RX] = 1;
sai->dl_mask[TX] = 1;
of_property_read_u32_index(np, "fsl,dl_mask", RX, &sai->dl_mask[RX]);
of_property_read_u32_index(np, "fsl,dl_mask", TX, &sai->dl_mask[TX]);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
......
......@@ -109,8 +109,8 @@
#define FSL_SAI_CR2_DIV_MASK 0xff
/* SAI Transmit and Receive Configuration 3 Register */
#define FSL_SAI_CR3_TRCE BIT(16)
#define FSL_SAI_CR3_TRCE_MASK GENMASK(16, 23)
#define FSL_SAI_CR3_TRCE(x) ((x) << 16)
#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16)
#define FSL_SAI_CR3_WDFL(x) (x)
#define FSL_SAI_CR3_WDFL_MASK 0x1f
......@@ -176,6 +176,8 @@ struct fsl_sai {
unsigned int slots;
unsigned int slot_width;
unsigned int dl_mask[2];
const struct fsl_sai_soc_data *soc_data;
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_dai_dma_data dma_params_tx;
......
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