1. 30 Sep, 2015 3 commits
  2. 28 Aug, 2015 1 commit
    • Paul Burton's avatar
      MIPS: CPS: use 32b accesses to GCRs · 90996511
      Paul Burton authored
      Commit b677bc03
      
       ("MIPS: cps-vec: Use macros for various arithmetics
      and memory operations") replaced various load & store instructions
      through cps-vec.S with the PTR_L & PTR_S macros. However it was somewhat
      overzealous in doing so for CM GCR accesses, since the bit width of the
      CM doesn't necessarily match that of the CPU. The registers accessed
      (GCR_CL_COHERENCE & GCR_CL_ID) should be safe to simply always access
      using 32b instructions, so do so in order to avoid issues when using a
      32b CM with a 64b CPU.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Cc: <stable@vger.kernel.org> # 3.16+
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: James Hogan <james.hogan@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/10864/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      90996511
  3. 09 Jul, 2015 5 commits
  4. 17 Feb, 2015 1 commit
  5. 24 Nov, 2014 1 commit
  6. 26 Aug, 2014 1 commit
  7. 19 Aug, 2014 1 commit
  8. 28 May, 2014 3 commits
    • Paul Burton's avatar
      MIPS: smp-cps: duplicate core0 CCA on secondary cores · 0155a065
      Paul Burton authored
      
      
      Rather than hardcoding CCA=0x5 for secondary cores, re-use the CCA from
      the boot CPU. This allows overrides of the CCA using the cca= kernel
      parameter to take effect on all CPUs for consistency.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      0155a065
    • Paul Burton's avatar
      MIPS: pm-cps: add PM state entry code for CPS systems · 3179d37e
      Paul Burton authored
      
      
      This patch adds code to generate entry & exit code for various low power
      states available on systems based around the MIPS Coherent Processing
      System architecture (ie. those with a Coherence Manager, Global
      Interrupt Controller & for >=CM2 a Cluster Power Controller). States
      supported are:
      
        - Non-coherent wait. This state first leaves the coherent domain and
          then executes a regular MIPS wait instruction. Power savings are
          found from the elimination of coherency interventions between the
          core and any other coherent requestors in the system.
      
        - Clock gated. This state leaves the coherent domain and then gates
          the clock input to the core. This removes all dynamic power from the
          core but leaves the core at the mercy of another to restart its
          clock. Register state is preserved, but the core can not service
          interrupts whilst its clock is gated.
      
        - Power gated. This deepest state removes all power input to the core.
          All register state is lost and the core will restart execution from
          its BEV when another core powers it back up. Because register state
          is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP
          implementation in order for the core to exit the state successfully.
      
      The code will detect which states are available on the current system
      during boot & generate the entry/exit code for those states. This will
      be used by cpuidle & hotplug implementations.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      3179d37e
    • Paul Burton's avatar
      MIPS: smp-cps: rework core/VPE initialisation · 245a7868
      Paul Burton authored
      
      
      When hotplug and/or a powered down idle state are supported cases will
      arise where a non-zero VPE must be brought online without VPE 0, and it
      where multiple VPEs must be onlined simultaneously. This patch prepares
      for that by:
      
        - Splitting struct boot_config into core & VPE boot config structures,
          allocated one per core or VPE respectively. This allows for multiple
          VPEs to be onlined simultaneously without clobbering each others
          configuration.
      
        - Indicating which VPEs should be online within a core at any given
          time using a bitmap. This allows multiple VPEs to be brought online
          simultaneously and also indicates to VPE 0 whether it should halt
          after starting any non-zero VPEs that should be online within the
          core. For example if all VPEs within a core are offlined via hotplug
          and the user onlines the second VPE within that core:
      
            1) The core will be powered up.
      
            2) VPE 0 will run from the BEV (ie. mips_cps_core_entry) to
               initialise the core.
      
            3) VPE 0 will start VPE 1 because its bit is set in the cores
               bitmap.
      
            4) VPE 0 will halt itself because its bit is clear in the cores
               bitmap.
      
        - Moving the core & VPE initialisation to assembly code which does not
          make any use of the stack. This is because if a non-zero VPE is to
          be brought online in a powered down core then when VPE 0 of that
          core runs it may not have a valid stack, and even if it did then
          it's messy to run through parts of generic kernel code on VPE 0
          before starting the correct VPE.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      245a7868
  9. 26 Mar, 2014 1 commit