1. 03 Jan, 2013 1 commit
    • Greg Kroah-Hartman's avatar
      ARM: drivers: remove __dev* attributes. · 351a102d
      Greg Kroah-Hartman authored
      CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
      markings need to be removed.
      This change removes the use of __devinit, __devexit_p, __devinitdata,
      and __devexit from these drivers.
      Based on patches originally written by Bill Pemberton, but redone by me
      in order to handle some of the coding style issues better, by hand.
      Cc: Bill Pemberton <wfp5p@virginia.edu>
      Cc: Russell King <linux@arm.linux.org.uk>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
  2. 09 Nov, 2012 3 commits
  3. 23 Aug, 2012 2 commits
    • Will Deacon's avatar
      ARM: perf: prepare for moving CPU PMU code into separate file · 6dbc0029
      Will Deacon authored
      The CPU PMU code is tightly coupled with generic ARM PMU handling code.
      This makes it cumbersome when trying to add support for other ARM PMUs
      (e.g. interconnect, L2 cache controller, bus) as the generic parts of
      the code are not readily reusable.
      This patch cleans up perf_event.c so that reusable code is exposed via
      header files to other potential PMU drivers. The CPU code is
      consistently named to identify it as such and also to prepare for moving
      it into a separate file.
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Will Deacon's avatar
      ARM: perf: probe devicetree in preference to current CPU · 04236f9f
      Will Deacon authored
      The CPU PMU is probed using the current cpuid information as part of the
      early_initcall initialising the architecture perf backend. For
      architectures without NMI (such as ARM), this does not need to be
      performed early and can be deferred to the driver probe callback. This
      also allows us to probe the devicetree in preference to parsing the
      current cpuid, which may be invalid on a big.LITTLE multi-cluster
      This patch defers the PMU probing and uses the devicetree information
      when available.
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
  4. 09 Jul, 2012 1 commit
    • Will Deacon's avatar
      ARM: 7448/1: perf: remove arm_perf_pmu_ids global enumeration · 4295b898
      Will Deacon authored
      In order to provide PMU name strings compatible with the OProfile
      user ABI, an enumeration of all PMUs is currently used by perf to
      identify each PMU uniquely. Unfortunately, this does not scale well
      in the presence of multiple PMUs and creates a single, global namespace
      across all PMUs in the system.
      This patch removes the enumeration and instead uses the name string
      for the PMU to map onto the OProfile variant. perf_pmu_name is
      implemented for CPU PMUs, which is all that OProfile cares about anyway.
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
  5. 09 May, 2012 1 commit
  6. 24 Mar, 2012 1 commit
  7. 07 Mar, 2012 3 commits
  8. 02 Feb, 2012 1 commit
  9. 02 Dec, 2011 2 commits
    • Will Deacon's avatar
      ARM: perf: add support for stalled cycle ABI events · 0445e7a5
      Will Deacon authored
      Commit 8f622422
       ("perf events: Add generic front-end and back-end
      stalled cycle event definitions") added two new ABI events for counting
      stalled cycles.
      This patch adds support for these new events to the ARM perf
      Cc: Jamie Iles <jamie@jamieiles.com>
      Cc: Jean Pihet <j-pihet@ti.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Will Deacon's avatar
      ARM: perf: clean and update ARMv7 event numbers · 4d301512
      Will Deacon authored
      This patch updates the ARMv7 perf event numbers so that:
      (1) A consistent naming scheme is used between different CPUs.
      (2) Only events actually used by Linux are described.
      (3) Where possible, architected events are used in preference to
          CPU-specific events.
      This results in the removal of a load of unused, hardcoded data and
      makes it more clear as to which events are supported on each PMU.
      Cc: Jean Pihet <j-pihet@ti.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
  10. 15 Oct, 2011 1 commit
  11. 31 Aug, 2011 9 commits
  12. 07 Jul, 2011 4 commits
  13. 01 Jul, 2011 2 commits
    • Peter Zijlstra's avatar
      perf, arch: Add generic NODE cache events · 89d6c0b5
      Peter Zijlstra authored
      Add a NODE level to the generic cache events which is used to measure
      local vs remote memory accesses. Like all other cache events, an
      ACCESS is HIT+MISS, if there is no way to distinguish between reads
      and writes do reads only etc..
      The below needs filling out for !x86 (which I filled out with
      unsupported events).
      I'm fairly sure ARM can leave it like that since it doesn't strike me as
      an architecture that even has NUMA support. SH might have something since
      it does appear to have some NUMA bits.
      Sparc64, PowerPC and MIPS certainly want a good look there since they
      clearly are NUMA capable.
      Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: David Miller <davem@davemloft.net>
      Cc: Anton Blanchard <anton@samba.org>
      Cc: David Daney <ddaney@caviumnetworks.com>
      Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Robert Richter <robert.richter@amd.com>
      Cc: Stephane Eranian <eranian@google.com>
      Link: http://lkml.kernel.org/r/1303508226.4865.8.camel@laptop
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
    • Peter Zijlstra's avatar
      perf: Remove the nmi parameter from the swevent and overflow interface · a8b0ca17
      Peter Zijlstra authored
      The nmi parameter indicated if we could do wakeups from the current
      context, if not, we would set some state and self-IPI and let the
      resulting interrupt do the wakeup.
      For the various event classes:
        - hardware: nmi=0; PMI is in fact an NMI or we run irq_work_run from
          the PMI-tail (ARM etc.)
        - tracepoint: nmi=0; since tracepoint could be from NMI context.
        - software: nmi=[0,1]; some, like the schedule thing cannot
          perform wakeups, and hence need 0.
      As one can see, there is very little nmi=1 usage, and the down-side of
      not using it is that on some platforms some software events can have a
      jiffy delay in wakeup (when arch_irq_work_raise isn't implemented).
      The up-side however is that we can remove the nmi parameter and save a
      bunch of conditionals in fast paths.
      Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Michael Cree <mcree@orcon.net.nz>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
      Cc: Anton Blanchard <anton@samba.org>
      Cc: Eric B Munson <emunson@mgebm.net>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Jason Wessel <jason.wessel@windriver.com>
      Cc: Don Zickus <dzickus@redhat.com>
      Link: http://lkml.kernel.org/n/tip-agjev8eu666tvknpb3iaj0fg@git.kernel.org
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
  14. 26 Mar, 2011 3 commits
  15. 04 Dec, 2010 2 commits
    • Will Deacon's avatar
      ARM: 6521/1: perf: use raw_spinlock_t for pmu_lock · 961ec6da
      Will Deacon authored
      For kernels built with PREEMPT_RT, critical sections protected
      by standard spinlocks are preemptible. This is not acceptable
      on perf as (a) we may be scheduled onto a different CPU whilst
      reading/writing banked PMU registers and (b) the latency when
      reading the PMU registers becomes unpredictable.
      This patch upgrades the pmu_lock spinlock to a raw_spinlock
      Reported-by: default avatarJamie Iles <jamie@jamieiles.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    • Will Deacon's avatar
      ARM: 6512/1: perf: fix warnings generated by sparse · 4d6b7a77
      Will Deacon authored
      Russell reported a number of warnings coming from sparse when
      checking the ARM perf_event.c files:
      | perf_event.c seems to also have problems too:
      |   CHECK   arch/arm/kernel/perf_event.c
      |   arch/arm/kernel/perf_event.c:37:1: warning: symbol 'pmu_lock' was not declared. Should it be static?
      |   arch/arm/kernel/perf_event.c:70:1: warning: symbol 'cpu_hw_events' was not declared. Should it be static?
      |   arch/arm/kernel/perf_event.c:1006:1: warning: symbol 'armv6pmu_enable_event' was not declared. Should it be static?
      |   arch/arm/kernel/perf_event.c:1113:1: warning: symbol 'armv6pmu_stop' was not declared. Should it be static?
      |   arch/arm/kernel/perf_event.c:1956:6: warning: symbol 'armv7pmu_enable_event' was not declared. Should it be static?
      |   arch/arm/kernel/perf_event.c:3072:14: warning: incorrect type in argument 1 (different address spaces)
      |   arch/arm/kernel/perf_event.c:3072:14:    expected void const volatile [noderef] <asn:1>*<noident>
      |   arch/arm/kernel/perf_event.c:3072:14:    got struct frame_tail *tail
      |   arch/arm/kernel/perf_event.c:3074:49: warning: incorrect type in argument 2 (different address spaces)
      |   arch/arm/kernel/perf_event.c:3074:49:    expected void const [noderef] <asn:1>*from
      |   arch/arm/kernel/perf_event.c:3074:49:    got struct frame_tail *tail
      This patch resolves these issues so we can live in silence
      Reported-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
  16. 25 Nov, 2010 1 commit
    • Will Deacon's avatar
      ARM: perf: separate PMU backends into multiple files · 43eab878
      Will Deacon authored
      The ARM perf_event.c file contains all PMU backends and, as new PMUs
      are introduced, will continue to grow.
      This patch follows the example of x86 and splits the PMU implementations
      into separate files which are then #included back into the main
      file. Compile-time guards are added to each PMU file to avoid compiling
      in code that is not relevant for the version of the architecture which
      we are targetting.
      Acked-by: default avatarJean Pihet <j-pihet@ti.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>