- 16 Sep, 2019 40 commits
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
This uses - our nwl mipi dsi controller driver - our mixel dphy driver - a forward port from NXPs dcss driver from our 4.18 tree (which we got from their 4.9/4.14 trees) - a forward port NXPs patches to the imx-display-subsystem driver from our 4.18 tree (which we got from their 4.9/4.14 trees)
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Guido Gunther authored
ctxld fails during boot due to its irqsteer dependency. Make us undo less stuff so that probing again works later on (instead of hanging the boot). TODO: check if this works on 4.18 too Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
We're returning != 0 on error Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
See 463659a0Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
According to 4.18 we have B0. Need to check what to do about busfreq Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Like in 1ef2917dSigned-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
like in f53705fdSigned-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
We don't have anything feeding these and they cause trouble when rebasing on linux-next so drop them. Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
from NXPs kernel Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
We don't need it atm. Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
This is just a hack until we have a proper solution. We don't want to allow userspace patch all kernel space. Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
0x14000 and 0x14018 are SRC_ADDR and DEST_ADDR in the BLT engine. 0x15C00 are the TX_DESCRIPTOR addresses on Halti5 at least. This avoids the etnaviv_warn_if_non_sensitive warnings. Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Otherwise we might end up with modules that can't be loaded: modprobe: ERROR: could not insert 'goodix': Unknown symbol in module, or unknown parameter (see dmesg) [ 15.190397] goodix: Unknown symbol touchscreen_report_pos (err -2) [ 15.221560] goodix: Unknown symbol touchscreen_parse_properties (err -2) [ 64.677545] goodix: Unknown symbol touchscreen_report_pos (err -2) [ 64.683767] goodix: Unknown symbol touchscreen_parse_properties (err -2) Signed-off-by:
Guido Günther <agx@sigxcpu.org>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
The mainline ATF doesn't currently support the FSL_SIP_GET_SOC_INFO call nor does it have the code to identify different imx8mq SOC revisions so mimic what NXPs ATF does here. As a fallback use ATF so we can identify new revisions once it gains support or when using NXPs ATF. Signed-off-by:
Guido Günther <agx@sigxcpu.org>
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Guido Gunther authored
This adds initial support for the NWL MIPI DSI Host controller found on i.MX8 SoCs. It adds support for the i.MX8MQ but the same IP can be found on i.MX8QXP. It has been tested on the Librem 5 devkit using DCSS. Co-developed-by:
Robert Chiras <robert.chiras@nxp.com> Signed-off-by:
Guido Günther <agx@sigxcpu.org>
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Guido Gunther authored
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 Socs. Signed-off-by:
Guido Günther <agx@sigxcpu.org>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Guido Gunther authored
Signed-off-by:
Guido Günther <guido.gunther@puri.sm>
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Angus Ainslie (Purism) authored
During the i2c probe the clock must be active Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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Angus Ainslie (Purism) authored
Need to be able to enable the camera so use a named gpio-led instead of an unnamed gpio. Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
Enable sound support for the devkit including the modem Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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Angus Ainslie (Purism) authored
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Angus Ainslie (Purism) authored
Connect the WoWWAN signal to a gpio key to wake the system Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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Angus Ainslie (Purism) authored
Use the 3v3 peripheral regulator instead of the pwr_en one Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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Angus Ainslie (Purism) authored
Specify all of the mclk's for the sai interfaces. Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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Angus Ainslie (Purism) authored
Set ausio PLL1 and PLL1 to use the correct parents Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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Angus Ainslie (Purism) authored
Enable the sai6 interface. Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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Angus Ainslie (Purism) authored
Add the simcomm modem and the sai6 interface that connects it. Signed-off-by:
Angus Ainslie (Purism) <angus@akkea.ca>
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Daniel Baluta authored
SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM) at the beginning of register address space. On imx7ulp FIFOs can held up to 16 x 32 bit samples. On imx8mq FIFOs can held up to 128 x 32 bit samples. Signed-off-by:
Daniel Baluta <daniel.baluta@nxp.com>
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Daniel Baluta authored
New IP version introduces Version ID and Parameter registers and optionally added Timestamp feature. VERID and PARAM registers are placed at the top of registers address space and some registers are shifted according to the following table: Tx/Rx data registers and Tx/Rx FIFO registers keep their addresses, all other registers are shifted by 8. SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map of the Reference Manual [1]. In order to make as less changes as possible we attach an offset to each register offset to each changed register definition. The offset is read from each board private data. [1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdfSigned-off-by:
Daniel Baluta <daniel.baluta@nxp.com>
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Daniel Baluta authored
This allows combining multiple-data-line FIFOs into a single-data-line FIFO. Signed-off-by:
Daniel Baluta <daniel.baluta@nxp.com>
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