Wire up interconnect for DCSS
This make sure we ramp up DRAM freq accordingly. Otherwise we fail to wake up after sleep showing an all cyan screen (which is an interesting effect on it's own).
I'm marking this as WIP since we currently switch to high bw mode on driver probe which makes us not clock down correctly until the first blank (thus wasting lots of battery). After that i see dram freq changing correctly and so far got a stable picture after every unblank.
I've folded in a fix to silence compile warnings in mhdp as well (that i've been dragging a long since some time)