nand_base.c 129 KB
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/*
 *  Overview:
 *   This is the generic MTD driver for NAND flash devices. It should be
 *   capable of working with almost all NAND chips currently available.
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 *
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 *	Additional technical information is available on
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 *	http://www.linux-mtd.infradead.org/doc/nand.html
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 *
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 *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
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 *		  2002-2006 Thomas Gleixner (tglx@linutronix.de)
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 *
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 *  Credits:
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 *	David Woodhouse for adding multichip support
 *
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 *	Aleph One Ltd. and Toby Churchill Ltd. for supporting the
 *	rework for 2K page size chips
 *
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 *  TODO:
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 *	Enable cached programming for 2k page size chips
 *	Check, if mtd->ecctype should be set to MTD_ECC_HW
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 *	if we have HW ECC support.
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 *	BBT table is not serialized, has to be fixed
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/module.h>
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#include <linux/delay.h>
#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/sched.h>
#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/nmi.h>
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#include <linux/types.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/nand_bch.h>
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#include <linux/interrupt.h>
#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/mtd/partitions.h>
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#include <linux/of.h>
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static int nand_get_device(struct mtd_info *mtd, int new_state);

static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
			     struct mtd_oob_ops *ops);
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/* Define default oob placement schemes for large and small page devices */
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static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
				 struct mtd_oob_region *oobregion)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	struct nand_ecc_ctrl *ecc = &chip->ecc;
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	if (section > 1)
		return -ERANGE;
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	if (!section) {
		oobregion->offset = 0;
		oobregion->length = 4;
	} else {
		oobregion->offset = 6;
		oobregion->length = ecc->total - 4;
	}
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	return 0;
}

static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
				  struct mtd_oob_region *oobregion)
{
	if (section > 1)
		return -ERANGE;
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	if (mtd->oobsize == 16) {
		if (section)
			return -ERANGE;

		oobregion->length = 8;
		oobregion->offset = 8;
	} else {
		oobregion->length = 2;
		if (!section)
			oobregion->offset = 3;
		else
			oobregion->offset = 6;
	}

	return 0;
}

const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
	.ecc = nand_ooblayout_ecc_sp,
	.free = nand_ooblayout_free_sp,
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};
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EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops);
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static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
				 struct mtd_oob_region *oobregion)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	struct nand_ecc_ctrl *ecc = &chip->ecc;
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	if (section)
		return -ERANGE;
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	oobregion->length = ecc->total;
	oobregion->offset = mtd->oobsize - oobregion->length;

	return 0;
}

static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
				  struct mtd_oob_region *oobregion)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	struct nand_ecc_ctrl *ecc = &chip->ecc;

	if (section)
		return -ERANGE;

	oobregion->length = mtd->oobsize - ecc->total - 2;
	oobregion->offset = 2;

	return 0;
}

const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
	.ecc = nand_ooblayout_ecc_lp,
	.free = nand_ooblayout_free_lp,
};
EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops);
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static int check_offs_len(struct mtd_info *mtd,
					loff_t ofs, uint64_t len)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	int ret = 0;

	/* Start address must align on block boundary */
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	if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
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		pr_debug("%s: unaligned address\n", __func__);
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		ret = -EINVAL;
	}

	/* Length must align on block boundary */
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	if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
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		pr_debug("%s: length not block aligned\n", __func__);
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		ret = -EINVAL;
	}

	return ret;
}

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/**
 * nand_release_device - [GENERIC] release chip
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 * @mtd: MTD device structure
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 *
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 * Release chip lock and wake up anyone waiting on the device.
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 */
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static void nand_release_device(struct mtd_info *mtd)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	/* Release the controller and the chip */
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	spin_lock(&chip->controller->lock);
	chip->controller->active = NULL;
	chip->state = FL_READY;
	wake_up(&chip->controller->wq);
	spin_unlock(&chip->controller->lock);
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}

/**
 * nand_read_byte - [DEFAULT] read one byte from the chip
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 * @mtd: MTD device structure
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 *
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 * Default read function for 8bit buswidth
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 */
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static uint8_t nand_read_byte(struct mtd_info *mtd)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	return readb(chip->IO_ADDR_R);
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}

/**
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 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
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 * @mtd: MTD device structure
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 *
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 * Default read function for 16bit buswidth with endianness conversion.
 *
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 */
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static uint8_t nand_read_byte16(struct mtd_info *mtd)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
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}

/**
 * nand_read_word - [DEFAULT] read one word from the chip
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 * @mtd: MTD device structure
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 *
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 * Default read function for 16bit buswidth without endianness conversion.
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 */
static u16 nand_read_word(struct mtd_info *mtd)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	return readw(chip->IO_ADDR_R);
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}

/**
 * nand_select_chip - [DEFAULT] control CE line
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 * @mtd: MTD device structure
 * @chipnr: chipnumber to select, -1 for deselect
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 *
 * Default select function for 1 chip devices.
 */
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static void nand_select_chip(struct mtd_info *mtd, int chipnr)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	switch (chipnr) {
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	case -1:
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		chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
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		break;
	case 0:
		break;

	default:
		BUG();
	}
}

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/**
 * nand_write_byte - [DEFAULT] write single byte to chip
 * @mtd: MTD device structure
 * @byte: value to write
 *
 * Default function to write a byte to I/O[7:0]
 */
static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	chip->write_buf(mtd, &byte, 1);
}

/**
 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
 * @mtd: MTD device structure
 * @byte: value to write
 *
 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
 */
static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	uint16_t word = byte;

	/*
	 * It's not entirely clear what should happen to I/O[15:8] when writing
	 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
	 *
	 *    When the host supports a 16-bit bus width, only data is
	 *    transferred at the 16-bit width. All address and command line
	 *    transfers shall use only the lower 8-bits of the data bus. During
	 *    command transfers, the host may place any value on the upper
	 *    8-bits of the data bus. During address transfers, the host shall
	 *    set the upper 8-bits of the data bus to 00h.
	 *
	 * One user of the write_byte callback is nand_onfi_set_features. The
	 * four parameters are specified to be written to I/O[7:0], but this is
	 * neither an address nor a command transfer. Let's assume a 0 on the
	 * upper I/O lines is OK.
	 */
	chip->write_buf(mtd, (uint8_t *)&word, 2);
}

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/**
 * nand_write_buf - [DEFAULT] write buffer to chip
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 * @mtd: MTD device structure
 * @buf: data buffer
 * @len: number of bytes to write
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 *
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 * Default write function for 8bit buswidth.
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 */
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static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	iowrite8_rep(chip->IO_ADDR_W, buf, len);
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}

/**
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 * nand_read_buf - [DEFAULT] read chip data into buffer
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 * @mtd: MTD device structure
 * @buf: buffer to store date
 * @len: number of bytes to read
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 *
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 * Default read function for 8bit buswidth.
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 */
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static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	ioread8_rep(chip->IO_ADDR_R, buf, len);
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}

/**
 * nand_write_buf16 - [DEFAULT] write buffer to chip
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 * @mtd: MTD device structure
 * @buf: data buffer
 * @len: number of bytes to write
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 *
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 * Default write function for 16bit buswidth.
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 */
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static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	u16 *p = (u16 *) buf;
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	iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
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}

/**
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 * nand_read_buf16 - [DEFAULT] read chip data into buffer
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 * @mtd: MTD device structure
 * @buf: buffer to store date
 * @len: number of bytes to read
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 *
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 * Default read function for 16bit buswidth.
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 */
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static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	u16 *p = (u16 *) buf;

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	ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
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}

/**
 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
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 * @mtd: MTD device structure
 * @ofs: offset from device start
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 *
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 * Check, if the block is bad.
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 */
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static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
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{
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	int page, res = 0, i = 0;
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	u16 bad;

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	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
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		ofs += mtd->erasesize - mtd->writesize;

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	page = (int)(ofs >> chip->page_shift) & chip->pagemask;

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	do {
		if (chip->options & NAND_BUSWIDTH_16) {
			chip->cmdfunc(mtd, NAND_CMD_READOOB,
					chip->badblockpos & 0xFE, page);
			bad = cpu_to_le16(chip->read_word(mtd));
			if (chip->badblockpos & 0x1)
				bad >>= 8;
			else
				bad &= 0xFF;
		} else {
			chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
					page);
			bad = chip->read_byte(mtd);
		}

		if (likely(chip->badblockbits == 8))
			res = bad != 0xFF;
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		else
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			res = hweight8(bad) < chip->badblockbits;
		ofs += mtd->writesize;
		page = (int)(ofs >> chip->page_shift) & chip->pagemask;
		i++;
	} while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
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	return res;
}

/**
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 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
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 * @mtd: MTD device structure
 * @ofs: offset from device start
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 *
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 * This is the default implementation, which can be overridden by a hardware
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 * specific driver. It provides the details for writing a bad block marker to a
 * block.
 */
static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	struct mtd_oob_ops ops;
	uint8_t buf[2] = { 0, 0 };
	int ret = 0, res, i = 0;

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	memset(&ops, 0, sizeof(ops));
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	ops.oobbuf = buf;
	ops.ooboffs = chip->badblockpos;
	if (chip->options & NAND_BUSWIDTH_16) {
		ops.ooboffs &= ~0x01;
		ops.len = ops.ooblen = 2;
	} else {
		ops.len = ops.ooblen = 1;
	}
	ops.mode = MTD_OPS_PLACE_OOB;

	/* Write to first/last page(s) if necessary */
	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
		ofs += mtd->erasesize - mtd->writesize;
	do {
		res = nand_do_write_oob(mtd, ofs, &ops);
		if (!ret)
			ret = res;

		i++;
		ofs += mtd->writesize;
	} while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);

	return ret;
}

/**
 * nand_block_markbad_lowlevel - mark a block bad
 * @mtd: MTD device structure
 * @ofs: offset from device start
 *
 * This function performs the generic NAND bad block marking steps (i.e., bad
 * block table(s) and/or marker(s)). We only allow the hardware driver to
 * specify how to write bad block markers to OOB (chip->block_markbad).
 *
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 * We try operations in the following order:
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 *  (1) erase the affected block, to allow OOB marker to be written cleanly
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 *  (2) write bad block marker to OOB area of affected block (unless flag
 *      NAND_BBT_NO_OOB_BBM is present)
 *  (3) update the BBT
 * Note that we retain the first error encountered in (2) or (3), finish the
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 * procedures, and dump the error in the end.
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*/
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static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	int res, ret = 0;
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	if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
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		struct erase_info einfo;

		/* Attempt erase before marking OOB */
		memset(&einfo, 0, sizeof(einfo));
		einfo.mtd = mtd;
		einfo.addr = ofs;
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		einfo.len = 1ULL << chip->phys_erase_shift;
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		nand_erase_nand(mtd, &einfo, 0);
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		/* Write bad block marker to OOB */
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		nand_get_device(mtd, FL_WRITING);
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		ret = chip->block_markbad(mtd, ofs);
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		nand_release_device(mtd);
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	}
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	/* Mark block bad in BBT */
	if (chip->bbt) {
		res = nand_markbad_bbt(mtd, ofs);
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		if (!ret)
			ret = res;
	}

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	if (!ret)
		mtd->ecc_stats.badblocks++;
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	return ret;
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}

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/**
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 * nand_check_wp - [GENERIC] check if the chip is write protected
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 * @mtd: MTD device structure
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 *
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 * Check, if the device is write protected. The function expects, that the
 * device is already selected.
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 */
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static int nand_check_wp(struct mtd_info *mtd)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	/* Broken xD cards report WP despite being writable */
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	if (chip->options & NAND_BROKEN_XD)
		return 0;

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	/* Check the WP bit */
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	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
	return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
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}

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/**
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 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
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 * @mtd: MTD device structure
 * @ofs: offset from device start
 *
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 * Check if the block is marked as reserved.
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 */
static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	if (!chip->bbt)
		return 0;
	/* Return info from the table */
	return nand_isreserved_bbt(mtd, ofs);
}

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/**
 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
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 * @mtd: MTD device structure
 * @ofs: offset from device start
 * @allowbbt: 1, if its allowed to access the bbt area
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 *
 * Check, if the block is bad. Either by reading the bad block table or
 * calling of the scan function.
 */
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static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	if (!chip->bbt)
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		return chip->block_bad(mtd, ofs);
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	/* Return info from the table */
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	return nand_isbad_bbt(mtd, ofs, allowbbt);
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}

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/**
 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
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 * @mtd: MTD device structure
 * @timeo: Timeout
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 *
 * Helper function for nand_wait_ready used when needing to wait in interrupt
 * context.
 */
static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	int i;

	/* Wait for the device to get ready */
	for (i = 0; i < timeo; i++) {
		if (chip->dev_ready(mtd))
			break;
		touch_softlockup_watchdog();
		mdelay(1);
	}
}

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/**
 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 * @mtd: MTD device structure
 *
 * Wait for the ready pin after a command, and warn if a timeout occurs.
 */
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void nand_wait_ready(struct mtd_info *mtd)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	unsigned long timeo = 400;
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	if (in_interrupt() || oops_in_progress)
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		return panic_nand_wait_ready(mtd, timeo);
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	/* Wait until command is processed or timeout occurs */
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	timeo = jiffies + msecs_to_jiffies(timeo);
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	do {
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		if (chip->dev_ready(mtd))
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			return;
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		cond_resched();
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	} while (time_before(jiffies, timeo));
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	if (!chip->dev_ready(mtd))
		pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
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}
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EXPORT_SYMBOL_GPL(nand_wait_ready);
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/**
 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
 * @mtd: MTD device structure
 * @timeo: Timeout in ms
 *
 * Wait for status ready (i.e. command done) or timeout.
 */
static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
{
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	register struct nand_chip *chip = mtd_to_nand(mtd);
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	timeo = jiffies + msecs_to_jiffies(timeo);
	do {
		if ((chip->read_byte(mtd) & NAND_STATUS_READY))
			break;
		touch_softlockup_watchdog();
	} while (time_before(jiffies, timeo));
};

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/**
 * nand_command - [DEFAULT] Send command to NAND device
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 * @mtd: MTD device structure
 * @command: the command to be sent
 * @column: the column address for this command, -1 if none
 * @page_addr: the page address for this command, -1 if none
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 *
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 * Send command to NAND device. This function is used for small page devices
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 * (512 Bytes per page).
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 */
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static void nand_command(struct mtd_info *mtd, unsigned int command,
			 int column, int page_addr)
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{
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	register struct nand_chip *chip = mtd_to_nand(mtd);
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	int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
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	/* Write out the command to the device */
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	if (command == NAND_CMD_SEQIN) {
		int readcmd;

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		if (column >= mtd->writesize) {
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			/* OOB area */
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			column -= mtd->writesize;
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			readcmd = NAND_CMD_READOOB;
		} else if (column < 256) {
			/* First 256 bytes --> READ0 */
			readcmd = NAND_CMD_READ0;
		} else {
			column -= 256;
			readcmd = NAND_CMD_READ1;
		}
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		chip->cmd_ctrl(mtd, readcmd, ctrl);
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		ctrl &= ~NAND_CTRL_CHANGE;
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	}
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	chip->cmd_ctrl(mtd, command, ctrl);
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	/* Address cycle, when necessary */
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	ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
	/* Serially input address */
	if (column != -1) {
		/* Adjust columns for 16 bit buswidth */
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		if (chip->options & NAND_BUSWIDTH_16 &&
				!nand_opcode_8bits(command))
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			column >>= 1;
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		chip->cmd_ctrl(mtd, column, ctrl);
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		ctrl &= ~NAND_CTRL_CHANGE;
	}
	if (page_addr != -1) {
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		chip->cmd_ctrl(mtd, page_addr, ctrl);
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		ctrl &= ~NAND_CTRL_CHANGE;
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		chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
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		/* One more address cycle for devices > 32MiB */
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		if (chip->chipsize > (32 << 20))
			chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
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	}
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	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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	/*
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	 * Program and erase have their own busy handlers status and sequential
	 * in needs no delay
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	 */
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	switch (command) {
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	case NAND_CMD_PAGEPROG:
	case NAND_CMD_ERASE1:
	case NAND_CMD_ERASE2:
	case NAND_CMD_SEQIN:
	case NAND_CMD_STATUS:
		return;

	case NAND_CMD_RESET:
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		if (chip->dev_ready)
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			break;
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		udelay(chip->chip_delay);
		chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
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			       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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		chip->cmd_ctrl(mtd,
			       NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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		/* EZ-NAND can take upto 250ms as per ONFi v4.0 */
		nand_wait_status_ready(mtd, 250);
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		return;

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		/* This applies to read commands */
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	default:
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		/*
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		 * If we don't have access to the busy pin, we apply the given
		 * command delay
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		 */
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		if (!chip->dev_ready) {
			udelay(chip->chip_delay);
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			return;
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		}
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	}
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	/*
	 * Apply this short delay always to ensure that we do wait tWB in
	 * any case on any machine.
	 */
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	ndelay(100);
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	nand_wait_ready(mtd);
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}

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static void nand_ccs_delay(struct nand_chip *chip)
{
	/*
	 * The controller already takes care of waiting for tCCS when the RNDIN
	 * or RNDOUT command is sent, return directly.
	 */
	if (!(chip->options & NAND_WAIT_TCCS))
		return;

	/*
	 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
	 * (which should be safe for all NANDs).
	 */
	if (chip->data_interface && chip->data_interface->timings.sdr.tCCS_min)
		ndelay(chip->data_interface->timings.sdr.tCCS_min / 1000);
	else
		ndelay(500);
}

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/**
 * nand_command_lp - [DEFAULT] Send command to NAND large page device
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 * @mtd: MTD device structure
 * @command: the command to be sent
 * @column: the column address for this command, -1 if none
 * @page_addr: the page address for this command, -1 if none
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 *
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 * Send command to NAND device. This is the version for the new large page
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 * devices. We don't have the separate regions as we have in the small page
 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
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 */
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static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
			    int column, int page_addr)
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{
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	register struct nand_chip *chip = mtd_to_nand(mtd);
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	/* Emulate NAND_CMD_READOOB */
	if (command == NAND_CMD_READOOB) {
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		column += mtd->writesize;
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		command = NAND_CMD_READ0;
	}
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	/* Command latch cycle */
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	chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
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	if (column != -1 || page_addr != -1) {
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		int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
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		/* Serially input address */
		if (column != -1) {
			/* Adjust columns for 16 bit buswidth */
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			if (chip->options & NAND_BUSWIDTH_16 &&
					!nand_opcode_8bits(command))
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				column >>= 1;
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			chip->cmd_ctrl(mtd, column, ctrl);
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			ctrl &= ~NAND_CTRL_CHANGE;
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			/* Only output a single addr cycle for 8bits opcodes. */
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			if (!nand_opcode_8bits(command))
				chip->cmd_ctrl(mtd, column >> 8, ctrl);
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		}
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		if (page_addr != -1) {
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			chip->cmd_ctrl(mtd, page_addr, ctrl);
			chip->cmd_ctrl(mtd, page_addr >> 8,
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				       NAND_NCE | NAND_ALE);
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			/* One more address cycle for devices > 128MiB */
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			if (chip->chipsize > (128 << 20))
				chip->cmd_ctrl(mtd, page_addr >> 16,
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					       NAND_NCE | NAND_ALE);
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		}
	}
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	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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	/*
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	 * Program and erase have their own busy handlers status, sequential
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	 * in and status need no delay.
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	 */
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	switch (command) {
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	case NAND_CMD_CACHEDPROG:
	case NAND_CMD_PAGEPROG:
	case NAND_CMD_ERASE1:
	case NAND_CMD_ERASE2:
	case NAND_CMD_SEQIN:
	case NAND_CMD_STATUS:
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		return;
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	case NAND_CMD_RNDIN:
		nand_ccs_delay(chip);
		return;

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	case NAND_CMD_RESET:
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		if (chip->dev_ready)
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			break;
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		udelay(chip->chip_delay);
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		chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
			       NAND_NCE | NAND_CTRL_CHANGE);
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		/* EZ-NAND can take upto 250ms as per ONFi v4.0 */
		nand_wait_status_ready(mtd, 250);
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		return;

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	case NAND_CMD_RNDOUT:
		/* No ready / busy check necessary */
		chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
			       NAND_NCE | NAND_CTRL_CHANGE);
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		nand_ccs_delay(chip);
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		return;

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	case NAND_CMD_READ0:
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		chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
			       NAND_NCE | NAND_CTRL_CHANGE);
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		/* This applies to read commands */
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	default:
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		/*
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		 * If we don't have access to the busy pin, we apply the given
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		 * command delay.
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		 */
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		if (!chip->dev_ready) {
			udelay(chip->chip_delay);
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			return;
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		}
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	}
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	/*
	 * Apply this short delay always to ensure that we do wait tWB in
	 * any case on any machine.
	 */
847
	ndelay(100);
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	nand_wait_ready(mtd);
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}

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/**
 * panic_nand_get_device - [GENERIC] Get chip for selected access
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 * @chip: the nand chip descriptor
 * @mtd: MTD device structure
 * @new_state: the state which is requested
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 *
 * Used when in panic, no locks are taken.
 */
static void panic_nand_get_device(struct nand_chip *chip,
		      struct mtd_info *mtd, int new_state)
{
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	/* Hardware controller shared among independent devices */
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	chip->controller->active = chip;
	chip->state = new_state;
}

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/**
 * nand_get_device - [GENERIC] Get chip for selected access
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 * @mtd: MTD device structure
 * @new_state: the state which is requested
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 *
 * Get the device and lock it for exclusive access
 */
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static int
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nand_get_device(struct mtd_info *mtd, int new_state)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	spinlock_t *lock = &chip->controller->lock;
	wait_queue_head_t *wq = &chip->controller->wq;
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	DECLARE_WAITQUEUE(wait, current);
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retry:
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	spin_lock(lock);

885
	/* Hardware controller shared among independent devices */
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	if (!chip->controller->active)
		chip->controller->active = chip;
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	if (chip->controller->active == chip && chip->state == FL_READY) {
		chip->state = new_state;
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		spin_unlock(lock);
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		return 0;
	}
	if (new_state == FL_PM_SUSPENDED) {
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		if (chip->controller->active->state == FL_PM_SUSPENDED) {
			chip->state = FL_PM_SUSPENDED;
			spin_unlock(lock);
			return 0;
		}
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	}
	set_current_state(TASK_UNINTERRUPTIBLE);
	add_wait_queue(wq, &wait);
	spin_unlock(lock);
	schedule();
	remove_wait_queue(wq, &wait);
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	goto retry;
}

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/**
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 * panic_nand_wait - [GENERIC] wait until the command is done
 * @mtd: MTD device structure
 * @chip: NAND chip structure
 * @timeo: timeout
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 *
 * Wait for command done. This is a helper function for nand_wait used when
 * we are in interrupt context. May happen when in panic and trying to write
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 * an oops through mtdoops.
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 */
static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
			    unsigned long timeo)
{
	int i;
	for (i = 0; i < timeo; i++) {
		if (chip->dev_ready) {
			if (chip->dev_ready(mtd))
				break;
		} else {
			if (chip->read_byte(mtd) & NAND_STATUS_READY)
				break;
		}
		mdelay(1);
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	}
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}

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/**
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 * nand_wait - [DEFAULT] wait until the command is done
 * @mtd: MTD device structure
 * @chip: NAND chip structure
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 *
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 * Wait for command done. This applies to erase and program only.
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 */
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static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
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{

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	int status;
	unsigned long timeo = 400;
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	/*
	 * Apply this short delay always to ensure that we do wait tWB in any
	 * case on any machine.
	 */
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	ndelay(100);
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	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
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	if (in_interrupt() || oops_in_progress)
		panic_nand_wait(mtd, chip, timeo);
	else {
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		timeo = jiffies + msecs_to_jiffies(timeo);
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		do {
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			if (chip->dev_ready) {
				if (chip->dev_ready(mtd))
					break;
			} else {
				if (chip->read_byte(mtd) & NAND_STATUS_READY)
					break;
			}
			cond_resched();
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		} while (time_before(jiffies, timeo));
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	}
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	status = (int)chip->read_byte(mtd);
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	/* This can happen if in case of timeout or buggy dev_ready */
	WARN_ON(!(status & NAND_STATUS_READY));
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	return status;
}

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/**
 * nand_reset_data_interface - Reset data interface and timings
 * @chip: The NAND chip
 *
 * Reset the Data interface and timings to ONFI mode 0.
 *
 * Returns 0 for success or negative error code otherwise.
 */
static int nand_reset_data_interface(struct nand_chip *chip)
{
	struct mtd_info *mtd = nand_to_mtd(chip);
	const struct nand_data_interface *conf;
	int ret;

	if (!chip->setup_data_interface)
		return 0;

	/*
	 * The ONFI specification says:
	 * "
	 * To transition from NV-DDR or NV-DDR2 to the SDR data
	 * interface, the host shall use the Reset (FFh) command
	 * using SDR timing mode 0. A device in any timing mode is
	 * required to recognize Reset (FFh) command issued in SDR
	 * timing mode 0.
	 * "
	 *
	 * Configure the data interface in SDR mode and set the
	 * timings to timing mode 0.
	 */

	conf = nand_get_default_data_interface();
	ret = chip->setup_data_interface(mtd, conf, false);
	if (ret)
		pr_err("Failed to configure data interface to SDR timing mode 0\n");

	return ret;
}

/**
 * nand_setup_data_interface - Setup the best data interface and timings
 * @chip: The NAND chip
 *
 * Find and configure the best data interface and NAND timings supported by
 * the chip and the driver.
 * First tries to retrieve supported timing modes from ONFI information,
 * and if the NAND chip does not support ONFI, relies on the
 * ->onfi_timing_mode_default specified in the nand_ids table.
 *
 * Returns 0 for success or negative error code otherwise.
 */
static int nand_setup_data_interface(struct nand_chip *chip)
{
	struct mtd_info *mtd = nand_to_mtd(chip);
	int ret;

	if (!chip->setup_data_interface || !chip->data_interface)
		return 0;

	/*
	 * Ensure the timing mode has been changed on the chip side
	 * before changing timings on the controller side.
	 */
	if (chip->onfi_version) {
		u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
			chip->onfi_timing_mode_default,
		};

		ret = chip->onfi_set_features(mtd, chip,
				ONFI_FEATURE_ADDR_TIMING_MODE,
				tmode_param);
		if (ret)
			goto err;
	}

	ret = chip->setup_data_interface(mtd, chip->data_interface, false);
err:
	return ret;
}

/**
 * nand_init_data_interface - find the best data interface and timings
 * @chip: The NAND chip
 *
 * Find the best data interface and NAND timings supported by the chip
 * and the driver.
 * First tries to retrieve supported timing modes from ONFI information,
 * and if the NAND chip does not support ONFI, relies on the
 * ->onfi_timing_mode_default specified in the nand_ids table. After this
 * function nand_chip->data_interface is initialized with the best timing mode
 * available.
 *
 * Returns 0 for success or negative error code otherwise.
 */
static int nand_init_data_interface(struct nand_chip *chip)
{
	struct mtd_info *mtd = nand_to_mtd(chip);
	int modes, mode, ret;

	if (!chip->setup_data_interface)
		return 0;

	/*
	 * First try to identify the best timings from ONFI parameters and
	 * if the NAND does not support ONFI, fallback to the default ONFI
	 * timing mode.
	 */
	modes = onfi_get_async_timing_mode(chip);
	if (modes == ONFI_TIMING_MODE_UNKNOWN) {
		if (!chip->onfi_timing_mode_default)
			return 0;

		modes = GENMASK(chip->onfi_timing_mode_default, 0);
	}

	chip->data_interface = kzalloc(sizeof(*chip->data_interface),
				       GFP_KERNEL);
	if (!chip->data_interface)
		return -ENOMEM;

	for (mode = fls(modes) - 1; mode >= 0; mode--) {
		ret = onfi_init_data_interface(chip, chip->data_interface,
					       NAND_SDR_IFACE, mode);
		if (ret)
			continue;

		ret = chip->setup_data_interface(mtd, chip->data_interface,
						 true);
		if (!ret) {
			chip->onfi_timing_mode_default = mode;
			break;
		}
	}

	return 0;
}

static void nand_release_data_interface(struct nand_chip *chip)
{
	kfree(chip->data_interface);
}

1120 1121 1122
/**
 * nand_reset - Reset and initialize a NAND device
 * @chip: The NAND chip
1123
 * @chipnr: Internal die id
1124 1125 1126
 *
 * Returns 0 for success or negative error code otherwise
 */
1127
int nand_reset(struct nand_chip *chip, int chipnr)
1128 1129
{
	struct mtd_info *mtd = nand_to_mtd(chip);
1130 1131 1132 1133 1134
	int ret;

	ret = nand_reset_data_interface(chip);
	if (ret)
		return ret;
1135

1136 1137 1138 1139 1140
	/*
	 * The CS line has to be released before we can apply the new NAND
	 * interface settings, hence this weird ->select_chip() dance.
	 */
	chip->select_chip(mtd, chipnr);
1141
	chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1142
	chip->select_chip(mtd, -1);
1143

1144
	chip->select_chip(mtd, chipnr);
1145
	ret = nand_setup_data_interface(chip);
1146
	chip->select_chip(mtd, -1);
1147 1148 1149
	if (ret)
		return ret;

1150 1151 1152
	return 0;
}

1153
/**
1154 1155 1156 1157
 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 * @mtd: mtd info
 * @ofs: offset to start unlock from
 * @len: length to unlock
1158 1159 1160 1161
 * @invert: when = 0, unlock the range of blocks within the lower and
 *                    upper boundary address
 *          when = 1, unlock the range of blocks outside the boundaries
 *                    of the lower and upper boundary address
1162
 *
1163
 * Returs unlock status.
1164 1165 1166 1167 1168 1169
 */
static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
					uint64_t len, int invert)
{
	int ret = 0;
	int status, page;
1170
	struct nand_chip *chip = mtd_to_nand(mtd);
1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183

	/* Submit address of first page to unlock */
	page = ofs >> chip->page_shift;
	chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);

	/* Submit address of last page to unlock */
	page = (ofs + len) >> chip->page_shift;
	chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
				(page | invert) & chip->pagemask);

	/* Call wait ready function */
	status = chip->waitfunc(mtd, chip);
	/* See if device thinks it succeeded */
1184
	if (status & NAND_STATUS_FAIL) {
1185
		pr_debug("%s: error status = 0x%08x\n",
1186 1187 1188 1189 1190 1191 1192 1193
					__func__, status);
		ret = -EIO;
	}

	return ret;
}

/**